Processor Watch

Issue #178 -- 07/26/2004

Editor: Tom R. Halfhill

In this issue:

Bulverde and Marathon Turn Cellphones Into PCs
Max Baron - Principal Analyst  {07/26/2004}

For a period of time, personal digital assistants (PDA) seemed to be stuck at delivering their simple personal manager information (PIM) functions, relying on slow 33MHz and 66MHz DragonBall applications processors. It took Intel’s first StrongARM chips at 206MHz and the 400MHz XScale family that followed them to advance PDAs to a level of performance that can offer modest support for PC-like applications. The new high-performance devices turned out to be influential enough to promote the increase of microprocessor frequencies in PDAs, and possibly the replacement of DragonBall by the ARM architecture.

Aimed unwisely by manufacturers at corporate customers and the additional few that could afford high-price high-end toys, the new PDAs languished on retailers’ shelves. PDA manufacturers tried to resuscitate the business via price reductions and by adding features such as support for digital cameras and wireless LAN communications, but their efforts were rewarded by disappointingly flat volume sales.

The PDA’s array of new features obtained by high microprocessor performance drew the attention of cellular phone manufacturers. The PDA and cellphone seemed destined to merge into one powerful (and expensive) appliance.

Intel, leader in the high-end PDA market, needed to refocus its XScale strategy to pursue more cellular phone design wins without losing its place in the PDA market. Intel’s development of Bulverde must have started more than two years ago already indicating the microprocessor manufacturer’s intentions to expand its business by supporting cellular and wireless LAN.

Microprocessor Report readers can access the full story (10+ pages, 9 graphics) here: www.mdronline.com/mpr/h/2004/0726/183001.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Toshiba’s New MIPS64 Family
Tom R. Halfhill - Senior Editor  {07/26/2004}

It’s been a relatively quiet year for MIPS-compatible processors, but Toshiba is making waves with a new family of high-performance embedded processors based on an enhanced MIPS64 core. The first member of the family is the TX9956CXBG, which has Toshiba’s new TX99/H4 64-bit core, jointly developed with MIPS Technologies.

Sampling now, with production scheduled to start in November, the TX9956CXBG is a standard-product chip for multifunction printers, high-end set-top boxes, automotive information systems, and other high-performance embedded applications. It’s a step up from Toshiba’s existing 64-bit MIPS processors, because the TX99/H4 is Toshiba’s first MIPS64-compatible core with superscalar pipelines and clock speeds beyond 500MHz. It’s also the first chip in its class, from any vendor, to be manufactured in a 90nm IC process, which gives the TX9956CXBG an advantage in power consumption and power-performance ratios.

In line with Toshiba’s historical practice, the TX9956CXBG—as the first member of a new family of standard products—is not a highly integrated chip. Instead, it’s a general-purpose processor designed to work with companion ASICs over its MIPS-compatible 32/64-bit System Address/Data (SysAD) bus. Future members of the TX99 family will be much more integrated. Toshiba plans to add such features as a PCI/PCI Express controller, memory controller, Gigabit Ethernet controller, NAND/NOR flash controller, cryptography accelerators, video ports, UARTs, timers, and other peripheral logic. Different members of the TX99 family will have different levels of integration, depending on their intended applications.

Microprocessor Report readers can access the full story (2+ pages, 1 graphic) here: www.mdronline.com/mpr/h/2004/0726/183002.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Welcome to the Electronic Design Forum
Jim McGregor -    {07/26/2004}

In this era of specialized conferences for each vendor or technology, In-Stat/MDR aspires to provide engineers and engineering management with a single source to learn about the key technologies that will determine the system architecture and form factor even before a design begins. These technologies include the processing element, core logic, operating system, design and programming tools, and interconnect architecture, to name but a few. The selection of each technology is driven not only by the system’s performance requirements and operating environment, but also by the technology’s maturity and by industry support, availability, price, performance, and standards. Given all these criteria, decisions are not easily made, but they are critical to the performance, cost, and life-cycle of the final product.

As part of our expanding scope, In-Stat/MDR is launching a new forum to explore the key technology options for electronic system design. The new forum, called the Electronic Design Forum (EDF), will be held October 7, 2004, following the Fall Processor Forum. This first forum will focus on interconnect options, including chip-, board-, and system-level interconnects.

The entire electronics industry is diligently working on new high-speed interconnects to solve the performance bottlenecks of older interconnect architectures. This effort, however, is leading to multiple alternatives with no clear winner. On one side, new chip interconnects will increase bandwidth while drastically changing the architecture of single-board computers and add-in cards. On the other side, new board and system interconnects will lead to new system architectures and network topologies. One new system architecture is AdvancedTCA (ATCA), which is designed to meet the performance and flexibility requirements of the telecommunications industry. ATCA consists of a base specification, which defines the electrical and mechanical standards, plus “dot” specifications, which define the use of various high-speed protocols, such as Advanced Switching, Fibre Channel, Gigabit Ethernet, InfiniBand, RapidFabric, and StarFabric. Consequently, engineers face a growing number of options, even within a single architecture.

The Electronic Design Forum will include representatives from industry leaders—such as AMCC, Broadcom, Cadence, FreeScale, IDT, PLX, Vitesse, and Xilinx—and trade associations discussing the use, application, and issues of these technologies in an effort to sort through the confusion. The morning will focus on the next generation of chip-level interconnects, and the afternoon will focus on board- and system-level interconnects. In addition, keynote presenters Tom Lagatta, group vice president for enterprise computing at Broadcom, and a representative from a major infrastructure provider (to be announced) will discuss the changes in system design that result from changes in technology and the outlook for the electronics industry with new technology enablers.

The Electronic Design Forum will be held at the San Jose Fairmont. More details on the event are available at www.mdronline.com/edf. Please join In-Stat/MDR as we explore the technology options for electronic system design.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

A Tale of Two Instructions
Tom R. Halfhill - Senior Editor  {07/19/2004}

Everyone has experienced the woe of cleaning out a closet and discarding something we needed later. Maybe it was something trivial, like a Pet Rock. Maybe it was something important, like a Pete Rose rookie card. Or maybe it was something both trivial and important, like the SAHF and LAHF instructions in the x86 microprocessor architecture.

Few closets are as messy as the x86 is. One problem is that several companies share the same crowded space. Another problem is that everyone keeps putting things into the x86 closet, but almost nobody ever takes things out. In a bold move, AMD recently tried to clean out the closet while installing a new 64-bit shelf. Unfortunately, AMD discarded two old instructions from the 16-bit days of the x86 that aren’t as obsolete as they seemed. Now AMD is making additional changes to put everything right again.

The most important changes are that future 64-bit processors from AMD—and perhaps from other x86 vendors, if everyone gets on the same page—will restore the two discarded instructions and define a new bit returned by the CPUID instruction. CPUID is the instruction that an operating system or user-level program can use to identify the computer’s processor and determine its capabilities.

Starting with new AMD64 processors coming later this year, CPUID will set a previously undefined bit in a general-purpose register to indicate whether the processor revives the SAHF and LAHF instructions that AMD mistakenly purged from 64-bit mode in AMD64. The strange story of the death and resurrection of these instructions is a classic example of the reason the x86 architecture has grown so complex over the past 26 years.

Microprocessor Report readers can access the full story (1+ pages) here: www.mdronline.com/mpr/h/2004/0719/182901.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

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