Processor Watch

Issue #179 -- 08/16/2004

Editor: Tom R. Halfhill  

In this issue:

Editorial: Who Really Deserves Credit for the New AMD?
Kevin Krewell - Senior Editor  {08/16/2004}

Electronic Business, another Reed Business Information publication, recently published a story on the transformation of AMD from an x86-processor follower to a leader (Electronic Business 7/1/04, “For Once, AMD Goes Its Own Way,” www.reed-electronics.com/eb-mag/article/CA430682?industryid=2116). The change in the perception of AMD has largely been tied to the success of the company’s 64-bit extensions to the x86 architecture and to the Opteron and Athlon 64 processors, which eschew clock frequency as the primary indicator of relative performance.

AMD originally referred to its 64-bit architecture as x86-64 but later renamed it AMD64. (See MPR 3/29/04-01, “AMD and Intel Harmonize on 64.”) Just as Intel had officially abandoned the “x86” label in favor of IA-32 (IA=Intel Architecture), AMD decided that the name of the 64-bit architecture should credit the inventors. Intel has lately been coerced by market forces to adopt the AMD extensions and forced by the limits of physics and thermodynamics to deemphasize clock frequency.

Despite all the praise heaped on the present AMD management, however, some past contributions may be underappreciated.

For one, AMD would be unable to deliver competitive processor systems without the help of third-party chip-set suppliers. During platform transitions, AMD itself has delivered chip sets that provide little more than basic functions. Of the third-party chip-set vendors, VIA and Nvidia have probably been the most influential in the success of the K6, Athlon, and Opteron processors. VIA has supported AMD with chip sets for many years; Nvidia was the right partner to help AMD break into the corporate PC market.

The present AMD management can also thank ex-CEO Jerry Sanders for his willingness to jettison almost every other product line in the company (excluding the profitable flash memory division) to keep his PC processor dreams alive. AMD sacrificed major market positions in networking components, communications chips, programmable logic, and embedded processors for the sake of the PC processor business. To the credit of Sanders, AMD has been the only x86 vendor to sustain more than single-digit market share against Intel over time.

Another company that has helped AMD is Microsoft. AMD really began to engage with Microsoft when AMD introduced the 3DNow SIMD extensions in the K6-2 processor. For AMD to be competitive in computer-game performance, AMD needed Microsoft to use 3DNow instruction optimizations in the Direct3D API. More recently, it was Microsoft’s endorsement of AMD64—and the private statements indicating Microsoft would support only one 64-bit x86 architecture—that eventually forced Intel to swallow the big, bitter pill that was AMD64. (For easier digestion, Intel has coated the pill with an Intel marketing name: EM64T.)

The final party that deserves thanks for AMD’s metamorphosis is…Intel.  That’s right, AMD’s archrival has done much to create the new, more independent AMD. The turning point for AMD was successfully negotiating in 1994–95 for a patent cross license and the right to use the MMX logo. It was at that critical juncture that AMD gave up socket compatibility (beyond the Pentium socket) in the negotiations with Intel.

For Intel, socket independence meant that AMD would no longer be able to drop x86 processors into Intel sockets by underselling Intel’s prices, a practice popularly called “socket stealing.” It was Intel’s annoyance with socket stealing that prompted then-CEO Andy Grove to famously dismiss AMD as the “Milli Vanilli of semiconductors” (a reference to a discredited singing duo of the 1980s that was found to be lip-synching to recordings made by other singers). Lacking socket compatibility, AMD could no longer count on the Intel infrastructure and would lose an important safety net. Intel probably didn’t believe AMD could marshal the resources necessary to create its own platform infrastructure, including a new processor-system bus, chip sets, motherboard designs, BIOS support, and system-software support from Microsoft.

Although it was a struggle, AMD extended the life of the Pentium socket (Socket 7 became Super7) and ultimately created its own bus by adapting DEC’s Alpha EV6 server/workstation bus for use in PCs. AMD evolved the EV6 bus from a design that required about 20 layers in the motherboard to a more economical six-layer design—and eventually to four-layer mass-market PC motherboards. The original Athlon (K7) processor with the EV6 bus marked AMD’s complete infrastructure independence from Intel.

Taiwan-based vendors VIA, ALi, and SiS eventually provided the dedicated chip-set support AMD needed. And they embraced AMD after Intel fought hard against them to bring chip-set sales in house. Later, Nvidia jumped on the AMD bandwagon after it was rumored that negotiations for a bus license with Intel had reached an impasse. Here, again, Intel’s positioning helped AMD. By holding out for too much from Nvidia, Intel pushed the company into an alliance with AMD. Although Taiwanese chip-set manufacturers had a mixed reputation with corporate buyers, the highly visible and respected Nvidia was considered a premium silicon supplier. Using an Nvidia chip set made it easier for AMD to break into the corporate PC market.

Finally, if Intel had not focused on a marketing strategy that equated Xeon with 32-bit processing and Itanium with 64-bit processing, the company could have responded to the AMD64 challenge much earlier—or even led the development. So when Intel tried to convince the industry to adopt the Itanium architecture for 64-bit processing, many saw the AMD64 alternative as more appealing and cost-effective.

Although Intel’s IA-64 Itanium architecture has many advantages (and more than a few of us thought it would eventually replace the x86), it’s not a panacea for all that’s wrong with IA-32. In addition, IA-64 hasn’t hit mainstream price points, its new features require all-new software, and it does a lousy job of running IA-32 code. Intel thought it had a well-integrated strategy for Xeon and Itanium, but the company actually left a critical gap between its two product lines—and AMD drove the Opteron processor into that gap like a wedge. The slow ramp of Itanium volumes provided another incentive for Microsoft to back the more evolutionary, and potentially higher-volume, 64-bit alternative from AMD.

To be sure, AMD still faces many challenges. Intel has an edge in fabrication technology and manufacturing capacity that AMD has been unable to match, even by partnering with companies like IBM and Motorola. Trends in power consumption and performance requirements have spurred Intel to create distinct x86 microarchitectures for desktop and mobile PC processors, but AMD is still tweaking the same basic microarchitecture to address both of those key markets. Intel has also been more aggressive at bringing new technologies like Hyper-Threading to PCs. And despite AMD’s recent victories, Intel still commands over 80% market share for PC processors.

Nevertheless, AMD is a good example of the axiom that whatever doesn’t kill you will make you stronger. AMD has learned from friend and foe alike how to be more independent and has gained confidence. Fighting and surviving against Intel has certainly become part of AMD’s corporate DNA—and some swagger is still left from the Jerry Sanders reign.

So, if AMD CEO Hector Ruiz ever runs into Intel CEO Craig Barrett, perhaps Ruiz should say, "Thanks for making us stronger, more independent." But I doubt he will.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

NX Helps Windows Security
Kevin Krewell - Senior Editor  {08/09/2004}

The original x86 (or IA-32, in Intel terminology) memory-protection scheme in the 8086 processor had separate segments for data, code, and stacks, with strict protection for each segment. Later, the 286 processor added four levels of security, with the kernel at ring 0 and user code at ring 3. But programmers widely disparaged the x86 segmentation scheme, and when Intel introduced memory paging in the 386 processor, the mix of segmentation and paging made an unacceptable brew. Operating-system programmers took to the paging scheme popular with Unix and avoided the x86’s segmentation, preferring a “flat” programming model.

The flat-memory model virtually eliminated the separation of code and data memory by initializing the code and data segments to exactly the same memory space. The paging scheme Windows, Linux, and various Unix flavors use does not allocate or bounds-check the code, data, or stack segments. In fact, AMD’s 64-bit mode for the x86 disables segmentation and ignores most of the segment attributes.

Unfortunately, the lack of these controls, and the use of weakly typed programming languages like C and C++, has inadvertently created vulnerable program code and a series of virus attacks on operating systems. Although the problem is mostly a software issue, the lack of a code-execution protection bit in the x86 protected-memory scheme was an oversight. Hardware changes were needed in x86 microprocessors to help stem the flood of software problems. As a result, x86 vendors are adding a No Execute (NX) bit to the x86 architecture.

Microsoft will probably use the NX bit in the following upcoming products and service packs (SP): the 32-bit edition of Windows XP SP2, the 32-bit Windows Server 2003 SP1, the 64-bit Windows Server 2003 for 64-bit Extended Systems, and the 64-bit Windows XP 64-Bit Edition for 64-bit Extended Systems.

AMD is the first vendor to deliver chips with the NX bit and refers to the capability as Enhanced Virus Protection. Intel is adding the NX bit to the Nocona and Prescott processors by early 4Q04 and will add support in the Pentium M (Centrino) processor in 1Q05. Intel will extend support for the NX bit to its Celeron processors, and AMD’s recently announced mobile Sempron has NX. Intel refers to NX as Execute Disable or XD, but it’s compatible with AMD’s implementation. Both VIA and Transmeta will add NX support in their latest processors, scheduled to ship in 2H04.

Microprocessor Report readers can access the full story (4 pages, 4 graphics) here: www.mdronline.com/mpr/h/2004/0809/183201.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Heterogeneous Multiprocessors Challenge Classic Engines
Max Baron - Principal Analyst  {08/02/2004}

It seems we see more advances in power management for general-purpose processor (GPP) and digital-signal processor (DSP) architectures than we do introductions of new concepts in architecture designed to combine high performance with power-efficient operation.

Responding to the challenge, 3Plus1 Technology has introduced a new "COOL" computer architecture intended to deliver high performance at low power. In fact, 3Plus1 Technology has chosen its name to reflect its target for the mobile processor markets: power, performance, and price, plus programmability. The fabless company expects to incorporate cores ("CoolProcessors") based on the new architecture in a line of chips aimed at different markets requiring real-time voice, video, and data-intensive processing.

The six-member chip family from 3Plus1, named "3Pxxxx," will initially be implemented in an industry-standard 130nm low-leakage process at an undisclosed foundry.

Microprocessor Report readers can access the full story (6 pages, 3 graphics) here: www.mdronline.com/mpr/h/2004/0802/183101.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

SPARC’s New Roadmap
Kevin Krewell - Senior Editor  {08/02/2004}

In April of this year, Sun Microsystems announced the discontinuation of two significant processor programs. The Millennium program was to be Sun’s UltraSparcV processor, and the Gemini program was to be the integrated dual-core processor.

With the elimination of the Millennium program, Sun created a large hole in its SPARC roadmap between UltraSparcIV+ and the Rock program, which was in only early-stage development and which Andy Ingram, vice president of marketing for Sun’s Scalable Systems Group, recently said won’t arrive until 2008. Then, in June, Sun dropped the other shoe, announcing the company had reached agreement with SPARC partner Fujitsu to collaborate on development and delivery of the next generation of SPARC processors. The combined systems effort of Fujitsu and Sun is code-named the Advanced Product Line (APL). When the APL family of systems ships, it will replace existing SPARC-based Sun Fire and PrimePower product lines. The Fujitsu PrimePower currently ships with the SPARC 64 V processor. Fujitsu will be announcing the 90nm shrink, named the SPARC 64 V+, and will be revealing plans for the next-generation multithreaded SPARC 64 VI at Fall Processor Forum (FPF) 2004 in October.

Sun and Fujitsu have been working together since the founding of SPARC International in 1989 by Sun, Fujitsu, and others. In 1999, Sun and Fujitsu signed the Interface Cross-license Agreement (covering the SPARC V9 instruction-set architecture), and the two companies signed the SPARC Joint Development Agreement. Combining the talents of Fujitsu and Sun makes a much stronger case for the survival of the SPARC architecture against the onslaught of Intel’s Itanium and IBM’s Power and from internal competition from Opteron systems.

Microprocessor Report readers can access the full story (3 pages, 3 graphics) here: www.mdronline.com/mpr/h/2004/0802/183102.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Most Recent Processor Watch Articles

Past Processor Watch Articles