Embedded Processor Watch

Editor: Jim Turley

In This Issue:

• Ten New Processors Announced at the Forum
• IBM Introduces Code Compression for PowerPC
• Motorola Unfolds Roadmap for Double ColdFire Performance
• Motorola Smoothes Upgrade Path from 68K to ColdFire
• STM Extends PC-On-A-Chip Line
• Industry Resources: Supercomputers Celebrate Tenth in Orlando
• New Embedded IC Announcements

Ten New Processors Announced at the Forum

The first annual Embedded Processor Forum saw 10 new embedded processors make their world debut. Coverage of these chips will follow in this and future issues of Embedded Processor Watch. Following is a list of the 10 announcements. Next year's Forum will be held in San Jose on May 3-6.

- Motorola ColdFire Version 4 (this issue)
- QED Alpine 64-bit MIPS Processor (future issue)
- Triscend E5 User-Configurable Microcontroller (future issue)
- Motorola MCore M300 (future issue)
- Hitachi SH3-DSP (future issue)
- Siemens TriCore Microcontroller/DSP (future issue)
- NEC V830R/NV (future issue)
- ARM ARM10 Processor Core (future issue)
- IBM PowerPC 405 Processor Core (this issue)
- SandCraft Montage MIPS Core (future issue)

IBM Introduces Code Compression for PowerPC

At last week's Embedded Processor Forum, IBM's chief architect for embedded PowerPC, Tom Sartorius, revealed that IBM has developed a code-compression system for embedded PowerPC chips that can shrink code size by as much as 40%. The code- compression system, called CodePack, is ready now. The first chip to use it should appear on the market in 2Q99.

IBM's CodePack is fundamentally different from ARM's Thumb or MIPS' MIPS-16 code- compression techniques. Rather than supplement the PowerPC instruction set with a second, 16-bit format, CodePack actually compresses object code, like running PKZip on a finished program. IBM claims a better overall compression ratio than its competitors, and CodePack can be applied to any PowerPC program or PowerPC chip, past, present, or future. It also does not interfere with software tools such as assemblers, compilers, or linkers.

CodePack uses an adaptive compression algorithm to squeeze the most out of each program. After the compressed object code is stored in memory, special CodePack hardware on the microprocessor decompresses the code in real time as it is fetched from memory but before it is executed. Although there is a slight performance penalty for this decompression, the extra latency is felt only during instruction- cache misses. Overall, CodePack is an interesting and unique approach to an old problem of minimizing the memory usage of high-performance embedded RISC processors.

Motorola Unfolds Roadmap for Double ColdFire Performance

Also at the Embedded Processor Forum, Motorola chief architect Joe Circello revealed the details of ColdFire Version 4 (v4), the next generation of mid-priced ColdFire processors due from Motorola in 2Q99. ColdFire v4 will double today's ColdFire performance, to 200 Dhrystone MIPS, through a combination of faster (150-MHz) clock rates, branch prediction, a Harvard bus structure, and an unusual form of "instruction folding."

ColdFire v4 also adds about 12 new instructions that are not found on current ColdFire chips. These include moves with sign-extend or zero-extend, signed saturate, branches with longer displacements, and better support for byte and word (16-bit) operands. A branch-prediction cache eliminates the delay for many changes of flow, and limited instruction folding collapses two assignment operators into one, improving performance. The new circuit changes and more aggressive, 0.25- micron, fabrication should boost ColdFire speeds enough to keep them competitive with the 32-bit RISCs.

ColdFire is already overtaking the venerable 68K family in performance. Today, many ColdFire chips are already faster than the fastest 68060 processor--at just a fraction of the price. Floating-point performance and backward software compatibility are the only things keeping the original 68K family alive. Designers generally prefer the much better price/performance of ColdFire for new designs.

Motorola Smoothes Upgrade Path from 68K to ColdFire

Coincident with its announcement of ColdFire v4 (see previous item), Motorola has finally dealt with a nagging issue and filled a gaping hole in the upgrade path from 68K processors to ColdFire processors. Although ColdFire and the 68K obviously share a common ancestry, they have never been binary compatible.

Two years ago, Motorola awakened to the possibility that programmers might want to port their code from the 68K to ColdFire, and provided (free of charge) an assembly- level source-code translator developed by MicroAPL.

This week, Motorola also announced a binary emulation library (also from MicroAPL) that fills the remaining potholes nicely. The emulation library traps unimplemented 68K instructions and emulates them on the ColdFire chip. Programmers can select which 68K processor they wish to emulate, and the library can be built accordingly. The minimum size of the library is about 50K of object code.

STM Extends PC-On-A-Chip Line

STMicroelectronics (STM; formerly SGS-Thomsen) has extended its line of all-in-one PC-on-a-chip processors with the STPC Industrial. Although there's little industrial about the chip except its temperature range (-40 degrees C to +85 degrees C), the new device does add "Super I/O" functions lacking from its predecessor, the STPC Consumer (see Microprocessor Report 8/4/97, p. 1). The STPC industrial has keyboard and mouse interfaces as well as PCI, ISA, and 486-local buses. The chip's 486 processor runs at 66, 75, or 80 MHz and has an 8K unified write-back cache.

The STPC Industrial follows the Consumer and Client variations, all of which are based on Cyrix's 486 CPU core. STM says future variations on the PC-on-a-chip theme will use other STM "internally developed" cores, but would not elaborate on whether the Metaflow design team it acquired some time ago meets that qualification. STM has no intention to market its embedded PCs to actual PC makers; even in the sub-$1000 market, PC buyers want more than 486DX-66 performance. Instead, the company believes the STPC's future lies in point-of-sale terminals, kiosks, and other embedded systems where software development tools and time-to-market are most the important thing.

Industry Resources: Supercomputers Celebrate Tenth in Orlando

The IEEE Computer Society and Association of Computing Machinery will host the tenth annual Supercomputer Conference (SC98) at the Orange County Convention Center in Orlando (Florida). The week-long conference, November 7-13, includes tutorials, papers, and a keynote address by Bran Ferren of Walt Disney Imagineering. The technical program will cover parallel computing, high-speed networking, cache coherence, numerical algorithms, and other topics.

Admission to the conference runs $390 for IEEE members; $500 for nonmembers. The tutorials cost extra. For more information, or to register, contact SC98 (La Jolla, Calif.) at 888.778.7298 or visit http://www.supercomp.org.

New Embedded IC Announcements

IS89C52 (ISSI) Microcontroller has 8051 core with 8K of on-chip flash memory, 40-MHz clock rate, 32 programmable I/O pins, UART, and three timers. Price: $4.50/1,000; Production: Now; Call ISSI at 408.588.0800.

PIC17C752 (Microchip) Microcontroller has 8-bit core, 16K of one-time programmable code storage, 678 bytes of data RAM, and 12-channel, 10-bit ADC. Price: $7.89/10,000; Samples: Now; Production: 3Q98; Call Microchip at 602.786.7668.

H8S/2144 (Hitachi) Microcontroller has 16-bit CPU, 128K of flash memory, 20-MHz clock frequency, and single 5-V supply; in 80-lead PQFP package. Price: $15.50/25,000; Production: Now; Call Hitachi at 800.285.1601.

CS8952 (Cirrus Logic) Ethernet transceiver handles 10/100-Mbps transmissions, operates from a single 5-V supply, and consumes 135 mA in normal operation. Price: $8/1,000; Production: Now; Call Cirrus at 512.912.3086.

CSP1152A (Lucent) Analog-to-digital converter includes dither function for use in wireless base stations; reduces extraneous signals up to 100 dB below max levels. Price: $35/50,000; Samples: Now; Production: 4Q98; Call Lucent at 800.372.2447.