Processor Watch

October 25, 2004

Editor: Tom R. Halfhill  

In this issue:

Embedded CPUs Zoom at FPF
Tom R. Halfhill - Senior Editor  {10/25/2004}

CPU cores in embedded processors are multiplying like rabbits and sprinting even faster. Four of the six presentations in the high-performance embedded session at Fall Processor Forum (FPF) 2004 described impressive new multicore designs. One new product family integrates up to 16 cores on a single chip. Clock speeds are soaring to 1.8GHz and beyond.

What’s going on? Networking and telecommunications. Although some other embedded applications require high-performance processors, the growing demands of packet routing, control-plane processing, and wireless infrastructures are forcing chip vendors to push their designs farther than ever before. While the advent of dual-core processors is generating enormous excitement in the PC market, most cutting-edge embedded processors now have at least two CPU cores. Some chip vendors are pursuing clock frequencies in the 2.0GHz range. Others use coprocessors and application-specific logic to boost performance. Indeed, the latest high-end embedded processors often employ all three of those tactics to some degree.

Six companies delivered presentations in the high-performance embedded-processor session at FPF, and the 13 chips they announced will compete almost head-to-head for the same customers, and frequently for the same applications. Their architectures are diverse but familiar: three product families are MIPS64 compatible, two are based on PowerPC, and one has an ARM-compatible core. The lack of proprietary CPU architectures is a notable departure from the heyday of network processors in the late 1990s. The vendors in this group have found other ways to distinguish themselves from the competition.

Applied Micro Circuits Corp. (AMCC) unveiled its first new PowerPC chip, the 440SPe I/O processor. AMCC recently became a PowerPC vendor by acquiring $227 million worth of chips, licenses, and design teams from IBM Microelectronics. (See the sidebar, “AMCC Strikes a Big Deal for PowerPC,” in MPR 4/26/04-02, “IBM Loosens Up CPU Licensing.”) AMCC is targeting the PowerPC 440SPe almost exclusively at network-storage applications, which sets it apart somewhat from the other new processors described in this session.

Broadcom announced a line of dual- and quad-core SiByte processors based on its efficient SB-1 MIPS64-compatible processor core. The quad-core BCM14xx chips are the latest incarnations of the long-delayed BCM1400, which Broadcom announced at Microprocessor Forum 2002. (See MPR 10/16/02-01, “Chip Combines Four 1GHz Cores.”) These will be the first Broadcom chips fabricated in a 90nm process, and they’re intended for control- and data-plane networking, network storage, wireless infrastructures, and high-density computing.

Cavium Networks revealed the first technical details of its groundbreaking Octeon family, announced a few weeks before FPF. These remarkable devices integrate 2 to 16 MIPS64-compatible processor cores per chip and establish a new data-plane networking category, the network services processor (NSP). For the first time, a single chip has the processing and I/O resources to handle L3–L7 packet routing, deep content filtering, and security. Microprocessor Report has already covered the Octeon family in depth. (See MPR 10/5/04-01, “Cavium Branches Out.”)

Faraday Technology announced its NetComposer-II, a networking processor intended for L4–L7 routing. Unlike the other chips in this FPF session, it’s a structured ASIC, not an ASSP. Three optional metal layers provide one million to three million programmable logic gates and 500Kb to 1.5Mb of SRAM. This technology allows designers to customize the chip with application-specific logic in a much shorter turnaround time than is possible with a conventional ASIC. Yet the programmable cells are much faster than FPGA logic, and the chip’s manufacturing cost is competitive with ASSPs. Faraday is using a custom-designed ARMv4-compatible processor core in this chip. (See MPR 5/18/04-02, “Risk Reduction, Faraday Style.”)

Freescale gave a detailed technical presentation on its first dual-core PowerPC chip and a single-core version of the part. The new PowerPC 8641D integrates two e600 CPU cores and is designed for L2–L4 routing, telecommunications, network storage, and general-purpose embedded applications. Clock frequencies will exceed 1.5GHz in a 90nm fabrication process, and the dual-core chip will compete directly with the latest multicore offerings from Broadcom and PMC-Sierra.

PMC-Sierra unveiled the RM11200, a dual-core MIPS64-compatible processor for routing, telecommunications, network storage, and general embedded applications. Its new E11K processor core is freshly ported to a 90nm fabrication process and is designed to hit 1.8GHz, the fastest clock speed announced in this session. The RM11200 will compete directly against the new multicore processors from archrivals Broadcom and Freescale.

All these chips are scheduled to enter production in 2H05 or 1H06. They will offer a formidable amount of processing power to embedded-systems designers; with so much variety to choose from, there’s something for just about everyone. The only drawback is that the multicore chips may pose an equally formidable programming challenge to operating-system vendors and software developers.

Microprocessor Report readers can access the full story (11+ pages, 8 figures) here: www.mdronline.com/mpr/h/2004/1025/184301.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

SPARC Turns 90nm
Kevin Krewell - Senior Editor  {10/25/2004}

At Fall Processor Forum 2004, we saw that developments in the SPARC architecture by the two main vendors of SPARC servers continue on track. In June of this year, Sun Microsystems and Fujitsu announced a codevelopment agreement. The new codeveloped product line is called Advanced Product Line (APL). That program will commence in 2006, but Sun is continuing to develop the dual-core UltraSPARC IV (US IV) family of dual-core processors. Likewise, long-time SPARC processor vendor Fujitsu showed early details of its next processor, the dual-core multithreaded SPARC 64 VI. Although Fujitsu has already shipped its 90nm SPARC 64 V+ (at 1.89GHz), Sun’s 90nm processor won’t ship until mid-2005. Thus, the two vendors have complementary and competing offerings. APL will consolidate the strengths of both organizations, but both sides must still do work to coordinate their differing technologies.

The new UltraSPARC IV+ (US IV+) processor is much more than a process shrink from 130nm to 90nm: it is a full second-generation dual-core design that was developed in parallel with the US IV. The design was implemented in the bulk silicon process of long-time Sun foundry partner TI. The chip layout is new, with a goal to double the performance of the US IV. Both the US IV and IV+ use single-threaded processor cores derived from the UltraSPARC III (US III). The frequency goal of the US IV+ is 1.8GHz initially, but later versions will be available at more than 2GHz. Other system goals of the US IV+ are to maintain full binary/system compatibility and extend the useful life of the Sun Fire Plane systems until the APL systems are available.

Fujitsu choose to wait until 90nm to make the dual-core SPARC 64 VI processor. Fujitsu is also taking an evolutionary approach with conservative design upgrades. The 90nm SPARC64 V+ is already shipping. Fujitsu is making quick progress in transitioning its processors from 130nm to 90nm and then to dual-core by reusing the same basic core and cache design, with mirroring of the design on the die.

Microprocessor Report readers can access the full story (6+ pages, 10 figures) here: www.mdronline.com/mpr/h/2004/1025/184302.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Editorial: First FPF Finale
Kevin Krewell - Senior Editor  {10/25/2004}

We’ve just completed our first Fall Processor Forum, the successor to Microprocessor Forum, and we are happy to report that paid attendance was up 15% over last year. We also had IBM’s Bernie Meyerson give our highest-rated keynote speech in recent memory. Bernie outlined the changes the industry is undergoing as we transition from system scaling, using “normal” semiconductor process shrinks, to an innovation-based scaling. I’ll have more on Bernie’s speech in a future story.

The program was packed with new and innovative processors from most key vendors in the field. You’ll be reading about them in stories this month and next. Multicore and multithreading processors were there in abundance and are the best indicators of the direction of future performance scaling.

We closed the Forum with a panel discussion on embedded x86 benchmarking that proved both controversial and productive. We’ll cover that discussion in a forthcoming story and will likely revisit the issue in future Forums as well. A benchmarking discussion would make a good birds-of-a-feather session at Spring Processor Forum 2005. We see a need to address the confusion AMD and Intel are creating with their model numbers and processor-numbering systems. Just wait till we get to the benchmarking issues of measuring and comparing the performance of dual-core processors with that of single-core processors running at higher clock speeds.

We have also begun some international expansion with a new Forum in Taiwan. By the time you read this editorial, that Forum will be over, but we have other locations in mind for 2005. Stay tuned for more information.

SpaceShipOne Makes Space History
While we were preparing for the Fall Processor Forum, space history was being made a few hundred miles away in Mojave, California. As a person who grew up watching the American space program unfold, with its Mercury, Gemini, and Apollo programs, I was the most excited I have been in years to see a private program reach for space and succeed. It’s also interesting to note that Burt’s SpaceShipOne contains less electronics than the typical automobile. Sometimes, it’s just better to stick to a KISS (keep it simple stupid) approach.

Burt Rutan, poster child for out-of-the-box thinking, designed, with funding from Microsoft cofounder Paul Allan, a unique craft that relied on a simple, but reliable, rocket motor and a unique approach to reentry that shifts the wings into a high-drag “shuttlecock” configuration that allows a controlled and low-heat reentry. Although the dead-stick (glider) landing doesn’t allow for more than one landing try, Burt’s pilots showed that even under less than optimal conditions, they can bring the ship in with relative ease, even at this experimental stage.

I guess the most important question is this: What took so long? Back in the 1960s, Stanley Kubrick and Arthur C. Clark’s movie 2001: A Space Odyssey showed private airlines running space shuttle operations. It seemed reasonable that industry would follow the government into space, but that transition never happened, and the space program became bogged down. We hope SpaceShipOne will become the true successor to Charles A. Lindbergh’s Spirit of St. Louis and will usher in a new era of affordable commercial space travel. I’m hoping they can get the price of a trip down to four digits before I’m too old to go!

Once Again: Is Intel in Serious Trouble?
With the cancellation of the 4GHz speed bump of the Pentium 4 processor, people in the industry are once more asking whether the wheels have come off the train. Although this situation is another very public embarrassment for Intel, we still believe the company’s long-term strategy of moving to multicore processors is sound and that its fab capacity is undiminished. The immediate challenge ahead for Intel will be holding off AMD’s market share advances in desktop and server processors during the transition; we believe Intel can maintain strong leadership in mobile computing.

Intel’s only concern in mobile would be if AMD acquired Transmeta: AMD could provide (relative) financial stability, and Transmeta’s Efficeon would fill a gap in AMD’s mobile product line. There are still many questions about such an acquisition, not the least of which is whether Transmeta would be worth the price at its present market value, and what AMD would do with yet another architecture and another design team. It might be possible, however, for the companies to work out an arrangement short of a merger.

In the meantime, Intel continues a series of missteps that have us perplexed. We are not in a position to recommend radical changes to Intel, but we have seen AMD was able to improve execution by combining the importation of fresh (outside) management; its small teams; work with outside consultants; and setting realistic goals. Intel has prided itself on tough, aggressive management and engineering excellence, but it may be a victim of its own success, with too many resources attacking too many markets. It is also possible that Intel’s management and engineering communities have become too inbred and need an infusion of outside DNA. (It should be noted that one of Intel’s more successful programs was the Pentium M processor, which came from an outlying design center in Israel.) Certainly, if Intel’s goal was to lower expectations for the company, it has succeeded.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Transmeta Extends Efficeon Roadmap
Kevin Krewell - Senior Editor  {10/18/2004}

The newest- (and second) version Efficeon processor is fabricated in Fujitsu’s 90nm process and is shipping in products today.

The first generation of Efficeon processors is built in TSMC 130nm and is shipping in a number of products, including notebooks from Sharp and HP server blades. The 1GHz 130nm Efficeon has a 7W TDP, similar to the older Crusoe processor.

Among the goals for the second-generation Efficeon are doubling performance and remaining pin compatible with first-generation parts. To do so, the design will go from 1GHz for the 130nm version to 2GHz or thereabouts in the Fujitsu 90nm process. By increasing the frequency target, Transmeta will have to increase the processor’s thermal envelope. But the 12–25W segment of the market is still the “thin and lite” segment that has experienced strong growth. The thin and lite notebook market is also much larger than the subnotebook and tablet PC markets in which Transmeta has competed to date. The first Efficeon-2 notebook, Sharp’s PC-MP70G, was launched in Japan on September 9, 2004. It uses a 1.6GHz Efficeon TM8800 processor.

In addition to moving Efficeon into a higher-power market, the new process will also allow Transmeta to cut power in half for 1GHz operation. The Efficeon has added the execute disable/no execute (NX) bit in the TLB table, which supports Microsoft’s Data Execution Prevention (DEP) feature in Windows XP Service Pack 2 (SP2), offering improved virus protection.

Microprocessor Report readers can access the full story (2+ pages, 3 figures) here: www.mdronline.com/mpr/h/2004/1018/184201.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

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