Embedded Processor Watch

Editor: Jim Turley

In This Issue:

• Triscend Announces Configurable Chips at Forum
• MIPS Technologies Opens Licensing Roadmap
• AMD K6 Goes Officially Embedded
• Triscend Adds ARM7 to Configurable Lineup
• Industry Resources: Embedded Processor Forum Call for Papers
• Industry Resources: IEEE Standards Available On-Line

Triscend Announces Configurable Chips at Forum

All microprocessors are programmable, but some, it seems, are more programmable than others. That is the thinking behind Triscend's new programmable microprocessor, the E5, which the company introduced at Embedded Processor Forum last month. The E5 combines popular a 8-bit architecture with an array of field-programmable logic to create a customizable controller for low-end embedded applications. The concept has been tried before--not always successfully--but Triscend's approach has some unique features that may help the E5 get a foothold in future markets.

Triscend's E5 is basically an 8032 microprocessor with some fixed peripherals and a large array of programmable logic. The CPU core is a licensed design and the peripherals are compatible with the dozens of 8032 derivatives that are already available. The CPU runs at 40 MHz-- quite fast for an 8-bit chip--and connects to the rest of the chip through a nonmultiplexed multimaster bus.

Where the E5 differs from other 8032-based microcontrollers is in its programmable logic. The first E5 chip is about 65% logic array, by silicon area. The field-programmable SRAM-based logic is used to create additional peripherals on demand. The logic array also allows E5 developers to reallocate most of the chip's external pins to suit their printed-circuit board layout. The first chip in the family, the TE520, provides about as much free logic as a Xilinx XC4013 or XCS30 FPGA. The TE520 also has 16K of SRAM, above and beyond the chip's programmable logic.

The E5 parallels the development of Motorola's ill-fated Core+ family of configurable processors (see Embedded Processor Watch #2). Like Triscend, Motorola believed in integrating processors and programmable logic. In Motorola's case, the Core+ parts were to have paired ColdFire with the company's fledgling FPGA architecture. The first chips were due in 3Q98, but scant months before their arrival, Motorola pulled the plug on Core+ and the FPGA architecture it was to be based on.

Configurability doesn't come cheap. In small (100-piece) quantities, Triscend is asking $55 for the TE520. This is a hefty $45 premium over run-of-the-mill 8032-based microcontrollers from Philips, Intel, Dallas, or others. Triscend is optimistic those prices can come down over the next four years.

Ultimately, Triscend's customers will be paying for convenience. The E5 family is a kind of insurance against unexpected product changes, delays, or capricious regulatory requirements. Time to market is the most important "feature" of many embedded systems, not price, performance, or power consumption. On that ground, Triscend's tools-- hardware and software--provide a lot of value. But as Motorola's example shows, that value proposition has a lot of challenges.

MIPS Technologies Opens Licensing Roadmap

MIPS Technologies took its first significant step as an independent company, unfolding its roadmap for future CPU cores and altering its licensing and distribution strategy. Henceforth, MIPS will be offering its cores in both synthesizable and hand-packed form, and not necessarily just to its eight licensed partners.

The company's roadmap shows three new MIPS cores, called Jade, Opal, and Ruby. Jade, at the low end, combines the R3000 microarchitecture with some R4000-style features, much as IDT did with its recently announced 32364 processor. The first Jade-based chips are expected to appear in 2Q99.

Opal is a full-on 64-bit design reminiscent of the R5000. MIPS is coy about Ruby, except to say that it will deliver "industry-leading performance;" it may be a superscalar design.

All three cores will initially be available (to MIPS licensees) in the traditional hard-layout format. Synthesizable versions would then follow by a few months, which is a first for MIPS Technologies but a growing trend in the industry. MIPS also revealed that it might distribute the new cores beyond just its inner circle of licensed semiconductor manufacturers. While the company is probably not ready to license directly to small, private engineers, it is considering approaching "market leaders" in specific areas. Such an approach might put MIPS at odds with its licensee partners, leading to friction, but may be the only way to survive against firms such as ARM, ARC, and Lexra as the CPU core market heats up.

AMD K6 Goes Officially Embedded

Like Intel, AMD has officially handed off responsibility for its former PC processor to its embedded group (see Embedded Processor Watch #19). In AMD's case, the chip in question is the K6, now called K6E. Also like Intel's Pentium/MMX, the chip is completely unchanged from its halcyon PC days.

In 1,000-unit quantities, the K6E is priced at $81 (233 MHz) or $84 (266 MHz), small discounts from the days of PC pricing. The tiny $3 difference in their prices reflects the infinitesimal difference in performance between these two chips and the fact the designers generally select one based on a convenient bus speed, rather than performance. As always, these K6 processors have their full floating-point unit, complete MMU, and Socket 7 compatibility.

AMD's price for its 266-MHz part is a good $20 (25%) cheaper than Intel's advertised price for a 266-MHz Pentium/MMX. Intel does not offer an "embedded" Pentium/MMX at 233 MHz, just a 166-MHz chip for $51. AMD's $81 part thus lies in between Intel's two offerings. AMD is not expected to ever offer its K5 processor for embedded applications. The K6 delivers better performance and costs AMD less to manufacture, leading to K5's swift departure from this world.

Triscend Adds ARM7 to Configurable Lineup

This morning, Triscend (http://www.triscend.com) announced a 32-bit sibling was on the way. Due in late 1999, a 32-bit version of the company's configurable processor (see earlier item) based on the ARM7TDMI core will be available, in addition to Triscend's existing 8032-based processors.

Unlike the 8-bit chips, the 32-bit Triscend processors will be built by Sharp in that company's 0.25-micron process. Sharp is already an ARM licensee; it was not necessary for Triscend to acquire an ARM license to offer the parts under its own name. The new addition should significantly expand Triscend's potential customer base by 2000.

Industry Resources: Embedded Processor Forum Call for Papers

We're looking for a few good microprocessors. The second annual Embedded Processor Forum will be held May 3-6 in San Jose (Calif.), and now is the time to submit significant new embedded chips for consideration. Proposals should be brief but identify the new embedded processor, DSP, or ASIC core that will be announced and describe what significant first- time technical detail will be disclosed. Proposals will be judged on technical interest as well as commercial significance.

Proposals can be submitted in confidence via e-mail addressed to mailto:EPFprogram@MDRonline.com. Final selection of proposals will take place, and winners will be notified, in December. The complete Call for Proposals is at http://www.MDRonline.com/events/empf/index.html.

Industry Resources: IEEE Standards Available On-Line

Starting last month, the IEEE is making its complete collection of bus architecture, microprocessor, and microcomputer standards available in an on-line subscription service. Subscribers will receive e-mail notification of new or updated standards, and can browse, download, and print standards documents.

More information is available from the IEEE by calling 732.562.3824 or at http://standards.ieee.org/catalog/olis/index.html.