Embedded Processor Watch

Editor: Jim Turley

In This Issue:

• Hitachi SH3-DSP Attacks Portable, Wireless, and VoIP
• SandCraft Shows Second Superscalar MIPS Core
• New Embedded IC Announcements
• Industry Resources: Portable Design Conference in San Diego
• Industry Resources: Explicit Chip Photos on the Web

Hitachi SH3-DSP Attacks Portable, Wireless, and VoIP

At October's Embedded Processor Forum, Hitachi revealed the latest version of its hybrid CPU/DSP architecture, SH3-DSP. As with the existing SH-DSP architecture (see Microprocessor Report 12/4/95, p. 10), the SH3-DSP merges a SuperH microprocessor with an integrated DSP coprocessor. The hybrid chip executes a single instruction stream from a unified instruction set, but SH3-DSP chips can execute one integer and one DSP operation in parallel with loads and stores. The first SH3-DSP chip, the SH7729, is sampling now at 133 MHz.

Internally, SH3-DSP chips have four buses: one for instructions, two for data transfers between the single register file and the dual ALUs, and an extra data bus for DMA transfers. As with Hitachi's earlier SH-DSP designs, on-chip memory is divided between cache and X and Y data memories, an organization familiar to DSP programmers.

The SH7729 chip has a 16K unified cache and another 16K of X/Y data memory. The chip's MMU makes it compatible with Windows CE, as are most SH-3 chips. A memory controller, four-channel DMA controller, timers, serial interfaces, and A/D and D/A converters round out the peripheral mix.

Voice-over-Internet-protocol (VoIP) has become a hot capability as the network companies jockey to compete with traditional telephone providers, catalyzing the development of DSP-enabled microprocessors. Hitachi has made a strong start in this area, faring better than ARM's Piccolo or the MIPS MDMX extensions. IBM's AltiVec was also designed, in part, for such applications and will certainly give Hitachi a run for its money at the high end (see Microprocessor Report 5/11/98, p. 1). SuperH's tight code size and low power consumption, along with Hitachi's demonstrated ability to mass-produce inexpensive parts, will all help the company distinguish itself amid the confusing whirl of merged microprocessor and DSP chips.

SandCraft Shows Second Superscalar MIPS Core

ASIC designers with a penchant for MIPS cores have been confronted with a plethora of products lately, and SandCraft intends to prolong the dilemma. At the recent Embedded Processor Forum, SandCraft president and founder Norman Yeung lifted the veil from the SR1, SandCraft's two-way superscalar 64-bit MIPS core for high-end ASIC development. The SR1 promises to overtake other MIPS cores from LSI Logic and compete directly against MIPS Technologies' own Opal and Ruby designs (see Embedded Processor Watch #21).

The SR1 boasts a total of six execution units including two integer units, a dedicated multiply-accumulate unit, a load/store unit, and a branch unit. The sixth execution unit, the FPU, is microarchitcturally separate from the others. It resides on the other side of the "MediaLink Bus," a SandCraft spin on the standard MIPS coprocessor interface.

The SR1, code-named Montage, is only the second design to emerge from SandCraft, (http://www.sandcraft.com), the small design firm that codeveloped NEC's high-end VR5464 processor (see Microprocessor Report 3/9/98, p. 1). SandCraft does not have a MIPS license, restricting its customer base to those companies that do.

As with ARM10 (see Embedded Processor Watch #23) and some other recent core designs, the instruction and data caches are an intrinsic part of the core. In the case of the SR1, those caches are each 16K in size, two-way set-associative, allow locking, and, in the case of the data cache, support both write-back and write-through updates. Interestingly, both caches also have parity protection (byte parity for the data cache; 32-bit word parity for the instruction cache). Cache parity is a relative rarity on any microprocessor and particularly unusual for a CPU core.

SandCraft has a tough road ahead of it. Although the MIPS architecture has proven hugely popular in recent years, there's also no shortage of suppliers filling that demand, and MIPS itself is about to enter the fray with its own CPU core macros. The cachet of the MIPS brand name may work against SandCraft, or it could work in the company's favor as licensees put off by MIPS's recent business moves find SandCraft a less threatening partner.

New Embedded IC Announcements

Si4132 (Silicon Laboratories) Dual-band RF-frequency synthesizer integrates RF PLL to decrease board space; works on 600 to 1,300-MHz and 1.3 to 1.6-GHz bands. Price: $6.50/10,000; Samples: Now; Production: 1Q99; Call Silicon Labs at 512.416.8500.

OV7500 (Omnivision) Color image sensor has NTSC/PAL composite-video encoder; outputs 408 x 492 image at 30 frames/s; needs 5-V supply and timing source. Price: $17/10,000; Production: Now; Call Omnivision at 408.733.3030.

OV7000 (Omnivision) Black-and-white image sensor has NTSC/PAL composite- video encoder; outputs 408 x 492 image at 30 frames/s. Price: $15/10,000; Production: Now; Call Omnivision at 408.733.3030.

OV7600 (Omnivision) Color image sensor with VGA resolution and A/D converters produces 640 x 480 image, with 8- or 16-bit digital parallel output. Price: $17/10,000; Production: Now; Call Omnivision at 408.733.3030.

MCRF250 (Microchip) Radio-frequency identification (RFID) chip has anticollision detection for passive 125-kHz RDIF applications; reader can interrogate 10 tags in same field. Price: $0.35/10,000; Production: Now; Call Microchip at 602.786.7286.

ZPSD813F1V (WSI) Support chip provides 128K of flash memory, 32K of EEPROM, 2K of SRAM, and 3,000 gates of programmable logic with MCU interface. Price: $8.95/25,000; Production: Now; Call WSI at 510.657.8495.

Industry Resources: Portable Design Conference in San Diego

The three-day "Portable Design '99" conference will be held at the San Diego Marriott Resort and Marina on February 2-4. The conference covers marketing and technical issues relating to portable instruments, cellular telephones, PDAs, and like equipment. Early registration (before 12/18) runs $575. For more information, contact Pennwell at 603.891.9267 or visit http://www.portable-design.com.

Industry Resources: Explicit Chip Photos on the Web

Unless your employer prohibits it, you can see and download graphic images of microprocessors at http://infopad.eecs.berkeley.edu/CIC/die_photos.