Embedded Processor Watch

Editor: Jim Turley

In This Issue:

• Siemens Builds First TriCore Chip
• QED Scales Bandwidth Heights with Alpine
• New Swedish Processor Has Customizable Instruction Set
• Industry Resources: Are You Behind the Wave?
• New Embedded IC Announcements

Siemens Builds First TriCore Chip

At the recent Embedded Processor Forum, Siemens revealed its first implementation of the hybrid DSP/microcontroller, TriCore. Design manager Rod Fleck explained that the initial test chips will be used to validate the TriCore architecture and debug TriCore development tools. TriCore targets applications that need a mixture of DSP and controller functions, such as cell phones, disk drives, and modems. In an unusual business strategy, Siemens will not only use TriCore in its own products, but will offer the core to customers for licensing.

TriCore is superscalar, with two main execution units: a 32-bit fixed- point data path and a load/store unit. The processor can issue up to three instructions per cycle, provided that one is for the data path, one is for the load/store unit, and one is a loop.

TriCore uses a mixture of 16- and 32-bit instructions, a technique intended to improve code density. To many programmers, code size is a greater concern than execution time. For control-oriented processing, TriCore provides a variety of logical operations (such as OR-NOT and AND-NOT) and bit-manipulation operations that are not usually seen on DSP processors.

The new TriCore chips run at a modest 33 MHz in Siemens' 0.35-mm, three- layer-metal process with embedded DRAM. Siemens expects to hit 80 MHz in mid-1999 using a 0.25-mm process. Benchmark results from Berkeley Design Technology (http://www.bdti.com) suggest that TriCore's DSP performance will be comparable to that of mainstream DSPs such as TI's TMS320C54x. TriCore's code density on control-oriented code appears to be comparable to that of other hybrid DSP/microcontrollers, such as Hitachi's SH-DSP.

Siemens has stated that the architecture of all future TriCore chips will be enhanced slightly over that used in the test chip. This move may be a reflection of Siemens' push to get initial silicon working as quickly as possible while final adjustments to the architecture were still in progress. At Embedded Processor Forum, Siemens hinted at a roadmap for TriCore that includes a floating-point version. [Thanks to Jennifer Eyre, BDTI--ed.]

QED Scales Bandwidth Heights with Alpine

With the same devotion many processor designers reserve for the CPU core, QED (http://www.qedinc.com) has developed an I/O structure that promises to double bus bandwidth over competing designs. At the recent Embedded Processor Forum, QED design manager Bill Fisher cleared the mists surrounding Alpine, the code name for the company's latest pair of processors.

The Alpine chips (technically, the RM5710 and RM5720) don't advance the state of the art in CPU design, but instead address bus bottlenecks. Both chips are based on QED's RM5261 processor core (see Embedded Processor Watch #7), attached to a 64-bit, 133-MHz SDRAM interface, a low-speed, 8-bit local peripheral bus, and one ('10) or two ('20) PCI buses. From a software perspective, the Alpine chips are no different from the RM5231, '61, or '71. To a hardware engineer, it's like night and day.

What makes the RM57xx chips interesting is their internal I/O management. The chips' PCI buses, local buses, and memory interfaces all have their traffic coordinated through a shared SRAM "buffer pool." There are five ports into the pool, with one for the CPU, the memory controller, and each of the two PCI interfaces. The fifth port is shared among the relatively low-speed ports: DMA, scratchpad, and local bus. All transactions are broken into two unconnected transfers: a write into the buffer pool and a read from the buffer pool.

At the Forum Fisher showed some evidence that Alpine can transfer data to/from PCI at 2x or 3x the rate of an equivalent RM5261 processor using a separate dual-PCI chip set. Transactions initiated by a PCI master to the processor's memory controller also showed a significant 20%-50% increase in bandwidth.

The RM5710 and '20 join a small clutch of processors with PCI buses. Alpine isn't intended for I2O like Intel's i960Rx parts; it's more of a central processor with access to high-end peripherals. QED invested a lot of effort in Alpine's buses and buffers; an investment that will pay off when future chips come with expanded I/O capabilities. Alpine is just the bedrock for a line of integrated controllers. When more peripheral controllers are added and bandwidth really becomes an issue, the value of QED's solid integration work will really peak.

New Swedish Processor Has Customizable Instruction Set

Everything old is new again. In the endless quest for performance, low cost, and tolerable Java performance, a Swedish startup company has resurrected the concept of rewritable microcode to produce a new embedded processor with a flexible, changeable instruction set. The new chip, which is sampling now, is intended for multifunction peripherals such as fax, copier, printer, and scanner equipment.

"NISC" and "WISC" are some of the fanciful terms suggested for this unusual embedded processor/controller. Parent company Imsys AB (Stockholm) has designed the new chip, dubbed the GP1000, for two roles. Conservatively, it's a low-cost (under $35), low-power (under 300 mW at 66 MHz) controller for office equipment. For that application, the GP1000 provides microcoded functions for scanning, image buffering, compression, decompression, halftone screening, printing, and other imaging tasks that normally would require high-level programming.

More ambitiously, Imsys has spun off a subsidiary called Clean Bean AB to market the chip's Java capabilities. By reprogramming the microcode to execute most Java bytecodes and some higher-level functions of a Java virtual machine (JVM), Imsys has created one of the few Java chips not derived from Sun Microelectronics' picoJava core. In this role, the GP1000 is aimed at smart appliances, hand-held computers, multifunction cell phones, point-of-sale terminals, and other intelligent devices.

Development of the chip was already well under way when Imsys engineer Roger Sundman wondered if the microcode could handle Java bytecode. Imsys engineers have already implemented most of the 226 Java bytecode instructions in microcode for the GP1000, but will probably stop short of implementing them all. In comparison, Sun's microJava 701 implements about 170 bytecode instructions in hardware, executes about 30 instructions in microcode, and traps the rest in software.

Rewritable microcode isn't a new idea, of course. The MVP CPU/16 had rewritable microcode, and the Burroughs B1700 had microcoded instruction sets for BASIC, FORTRAN, COBOL, and RPG-II. Patriot Scientific's PSC1000 (aka ShBoom) executes Java in microcode, and even Intel's Pentium II processors have a tiny amount of rewritable microcode to allow limited patches.

Among embedded processors, the GP1000's combination of rewritable microcode, low-level concurrency, support for image processing, and multiple register banks is unique. It will be interesting to see how fully Imsys's customers take advantage of these capabilities. [Thanks to Tom Halfhill--ed.]

Industry Resources: Are You Behind the Wave?

John Latta's "Wave Report" is a free e-mail newsletter (not unlike this one) that is published on an irregular, as-needed basis. The Wave Report, and Dr. Latta's firm behind it, 4th Wave, focuses on industry developments in 3D and multimedia technology. Affected product categories include PCs, information appliances, consumer electronics, and communications.

Subscriptions to the Wave Report are free. For more information, or to subscribe, visit http://fourthwave.com/wave.

New Embedded IC Announcements

uPD78094xGF, uPD780814xGK (NEC) K0-family 8-bit microcontrollers have Direct Storage CAN interfaces with extended-frame format capability at up to 500 kbps. Price: $9.90/10,000; Production: Now.

PCI4450 (TI) CardBus controller and IEEE-1394a host controller in a single chip; saves board space and includes Zoom Video buffers and programmable pins. Price: $20/1,000; Samples--1Q99; Production: 1Q99; Call TI at 800.477.8924.

JT1001 (JATO Technologies) Network controller for 10/100/1000-Mbps Ethernet handles IPv4 checksum calculation on chip, with PCI bus interface, packet bursting. Price: $65/1,000; Production: Now; Call JATO at 512.407.2100.

THS7002 (TI) Amplifier for ADSL receivers has programmable gain to compensate for line length and other conditions; with clamp protection. Price: $5.79/1,000; Samples: Now; Production: 1Q99; Call TI at 800.477.8924.

OV511 (OmniVision) Controller chip connects digital CMOS image sensors to USB; needs only 256K of DRAM and USB transceiver for low-cost digital camera. Price: $5/10,000; Call OmniVision at 408.733.3030.

AT49BV1604, AT49BV1614 (Atmel) Flash memory devices have concurrent read-while-write feature; two banks allow reading from one while writing to the other. Price: $8.10/10,000; Production: Now; Call Atmel at 408.441.0311.

CXK77V80160TM-9 (Sony) Static RAM has 16-Mbit capacity, organized as 2Mx8, with 9-ns (111-MHz) access time; in 78-lead TSOP II package. Price: $200/10,000; Production: Now; Call Sony at 800.222.7669.