Embedded Processor Watch

Editor: Jim Turley

In This Issue:

• MIPS Signs Texas Instruments
• Tensilica Debuts Configurable Processor Architecture
• Industry Resources: Los Angeles Goes to HEC
• Industry Resources: Semiconductor Fabrication by the Book
• New Embedded IC Announcements

MIPS Signs Texas Instruments

MIPS Technologies has signed DSP powerhouse Texas Instruments as its newest licensee. TI will use MIPS processor cores in future "system- level integration" devices that combine the CPU with TI's own DSP cores. TI will also make the MIPS cores available to its ASIC customers as early as next month.

TI has signed on for the Jade and Opal processor cores (see Embedded Processor Watch #21), MIPS's forthcoming low-end (32-bit) and midrange (64-bit) processor designs. Jade, which will be disclosed more fully at Embedded Processor Forum in May, brings general-purpose computing and Windows CE compatibility to the TI product line, something TI has historically lacked. MIPS is not the first processor core that TI has licensed; the company also has licenses for ARM (http://www.arm.com) and ARC Cores's (http://www.arccores.com) processors.

TI hinted at plans for highly integrated devices based on the new MIPS cores that could combine TI's strengths in DSP, mixed-signal, and connectivity (i.e., FireWire and USB) with the MIPS processors. The first such devices would likely combine the Jade CPU with a DSP from TI's 'C54x family.

The combination of MIPS processors and TI's well-supported DSP architectures should prove a daunting combination that is especially well-suited for portable or handheld devices with wireless communication. No schedule was given for product introductions, and although ASIC designs could start shortly, real products are not likely before the end of this year.

Tensilica Debuts Configurable Processor Architecture

Proving there's no shortage of new ideas in processor design, Silicon Valley startup Tensilica (http://www.tensilica.com) has made its first public announcement of its new processor design. Tensilica's CPU core differs from those of, say, PowerPC or SPARC in that it can be configured and customized by an individual ASIC developer. That is, Tensilica provides the "core" CPU design along with the design tools for ASIC developers to create their own extensions to the instruction set.

Tensilica's RISC-inspired processor design mixes 16-bit and 24-bit instructions, an orthogonal register file, and about 70 immutable "base case" instructions. Customers are then free to add their own special- purpose instructions by defining them using a subset of the Verilog hardware-description language. The resulting mix is then synthesized and fabricated as part of a larger ASIC design. Developers can create any new functions they desire, as long as they can be encoded in 24 bits, execute in one clock cycle, and use the hardware resources of the basic Tensilica ALU.

Tensilica is staffed by ex-MIPS alumni Earl Killian and Chris Rowen, and ex-Synopsys personnel Harvey Jones, Bernie Rosenthal, and Albery Wang. The company's business model is similar to those of MIPS, ARC Cores, ARM, and other IP-licensing companies. Tensilica licenses VHDL or Verilog descriptions of its design, plus the customization tools, to ASIC designers. Licensees pay an up-front fee, plus royalties on shipping products.

Tensilica is one of a growing class of processor (or processor-IP) companies basing its strategy on the widening gap between what semiconductor technology can produce and what customers need. TeraGen (http://www.tera-gen.com; see Embedded Processor Watch #32), Triscend (http://www.triscend.com; see Embedded Processor Watch #21), Lexra (http://www.lexra.com; see Embedded Processor Watch #10), Scenix (http://www.scenix.com; see Embedded Processor Watch #25), and ARC Cores (http://www.arccores.com; see Embedded Processor Watch #19) all peddle processors that are configurable in one way or another. Each converts "excess" clock speed or circuit density into flexibility or configurability. The future undoubtedly holds even more such advances; in the meantime, embedded customers and ASIC developers have an ever broader choice among microprocessor architectures--including their own.

Industry Resources: Los Angeles Goes to HEC

WinHEC, that is, the annual Windows Hardware Engineering Conference, to be held in the Los Angeles Convention Center April 7-9. Makers, designers, and purchasers of Windows hardware (commonly called PCs) will congregate to hear Microsoft executives Steve Ballmer, Brian Valentine, David Cole, Carl Stork, Jay Torborg, and others pronounce on the future of Windows and the systems that run it. Intel's Pat Gelsinger and MicroDesign Resources founder Michael Slater will also be presenting on hardware directions and design trends.

In addition to the presentations and general sessions there will be technical sessions covering system architecture, modem and audio integration, mobile platforms, embedded, security, and encourangingly, a session on quality and simplicity.

Early registration (before 2/19) runs $995 for the whole shooting match; passes for the evening soirees only are $35. For more information, or to register, call 800.254.5509 or direct your built-in browser to http://www.microsoft.com/winhec.

Industry Resources: Semiconductor Fabrication by the Book

Integrated Circuit Engineering (ICE) has released "Advanced Semiconductor Fabrication Handbook: Putting the Deep Submicron Puzzle Together," an imposing tome covering the self-evident topic. New chapters cover copper metalization as well as the usual topics of low-k dielectrics, Damascene processing, crystallography and preparation, deposited films, and planarization processes. Not for the faint of heart.

A copy of the book, plus CD-ROM, sells for $995 (additional copies $695). To order, contact ICE (Scottsdale, Ariz.) at 602.515.4260 or stop by http://www.ice-corp.com.

New Embedded IC Announcements

ZPSD813F1V (WSI) Flash MCU integrates 128 K of flash memory, 32 K of EEPROM, 2 K of SRAM; operating at 2 MHz, drawing 1.6 mA. Price: $8.95/25,000; Production: Now; Call WSI at 510.498.1723.

M40Z300/W (STMicroelectronics) Non-Volatile RAM controller converts low power SRAMs into NVRAMs; with reset output for power-on reset; in 28-pin SOIC package. Price: $4.25/100,000; Production: Now; Call ST at 781.861.2650.

70V3579, 70V3569 (IDT) Synchronous dual-port SRAM chips are organized as 32Kx36 ('79) or 16Kx36 ('69) with 3.3-V supplies and 100-MHz data rates. Price: $39.95/10,000; Samples: Now; Production: 3Q99; Call IDT at 800.345.7015.

70V3389, 70V3379 (IDT) Synchronous dual-port SRAM chips are organized as 64Kx18 ('89) or 32Kx18 ('79) with 3.3-V supplies and 100-MHz data rates. Price: $39.95/10,000; Samples: Now; Production: 3Q99; Call IDT at 800.345.7015.