Embedded Processor Watch

Editor: Tom Halfhill

In This Issue:

• Fujitsu FR-V Architecture Bets On VLIW
• LX4280 Fills Lexra's Midrange
• Industry Resources: Microprocessor Forum Agenda Disclosed
• Embedded IC Announcements

Fujitsu FR-V Architecture Bets On VLIW

Fujitsu Microelectronics has announced a new embedded-processor architecture that's definitely buzzword compliant. It has very long instruction words (VLIW), multimedia instructions, digital-signal-processing (DSP) features, a customer-extensible instruction set, and configurable cores. And the cores are designed to be combined with macro libraries to build system-on-a-chip (SOC) parts for consumer electronics, automotive-navigation computers, and communication devices.

Although Fujitsu (http://www.fujitsu.com/micro.html) won't disclose the full details about the new FR-V architecture until Microprocessor Forum in October, the company has sketched out the basics. FR-V builds on Fujitsu's considerable experience with FR-series microcontrollers, SparcLite processors, and supercomputer compilers. The goal is to provide a highly configurable architecture that's efficient enough for small, battery-powered products (such as cell phones and digital cameras) yet powerful enough for compute-intensive applications (such as digital TV, 3D graphics, and speech recognition).

Fujitsu is working on two FR-V cores: the FR500, which has a four-way VLIW microarchitecture for higher-performance applications, and the FR300, which has a two-way VLIW design that's optimized for low power consumption -- and in particular, for use in cell phones. Fujitsu says the FR500 will be available in December and will cost less than $25 in 10,000-unit quantities. Fujitsu expects FR300-based chips to cost less than $12 in 10,000-unit quantities when they enter production in 2001.

VLIW is an unconventional architecture for embedded processors. Developers will have to rely more heavily on high-level language compilers than ever before. If the compilers have trouble scheduling instructions for parallel execution and pad the instruction words with too many NOPs, the resulting code bloat will inflate memory requirements, system costs, and power consumption -- all critical considerations for embedded systems. As Fujitsu discloses more details, it will be interesting to see how the FR-V architecture addresses those challenges.--T.R.H. (The full version of this article appeared in the August 2 issue of Microprocessor Report.)

LX4280 Fills Lexra's Midrange

Lexra (http://www.lexra.com) has announced a MIPS-compatible embedded processor core that it claims will be the fastest such 32-bit core on the market. The new LX4280 is expected to deliver 275 Dhrystone MIPS at a worst-case clock frequency of 200 MHz. At its maximum estimated frequency of 266 MHz, the LX4280 should deliver at least 350 MIPS.

That's up to 35% faster than Lexra's own LX4180 and about 70% faster than the maximum estimated performance of the new MIPS32 4Kc "Jade" core from Mips Technologies (see Embedded Processor Watch #51, http://www.MDRonline.com/q/epw/issues/epw_51.html).

Performance comparisons are tricky, however, because Lexra is estimating the LX4280's frequency range in a 0.18-micron process, while Mips is expecting the 4Kc to run at 150-225 MHz in a 0.25-micron process. The race will be closer when the 4Kc is ported to a comparable geometry, although the single-issue Mips core will still be at a disadvantage because the LX4280 has dual-issue integer pipelines. Embedded-system designers who need greater code density will also appreciate Lexra's support for the condensed MIPS-16 instruction set -- a feature that Mips omitted from the new Jade cores.

Lexra plans to deliver the LX4280 as a synthesizable RTL model in 4Q99 and as a "SmoothCore" -- Lexra's term for an optimized hard macro -- in 1Q00. Lexra's foundry partners include IBM, TSMC, and UMC.--T.R.H. (The full version of this article appeared in the August 2 issue of Microprocessor Report.)

Industry Resources: Microprocessor Forum Agenda Disclosed

Full details on the 1999 Microprocessor Forum program are available now at http://www.MDRonline.com/mpf/. The program includes:

• Keynote presentations from John Hennessy, cofounder of MIPS and Provost at Stanford University, and Ken Kutaragi, President and CEO of Sony Computer Entertainment
• New embedded processors, including National's information appliance on a chip (Geode SC1400), the new SH-5 architecture from Hitachi and STMicroelectronics, a 64-bit core from MIPS, and a superscalar embedded PowerPC core from IBM
• Leading-edge DSPs from Massana, Zoran, and Analog Devices
• Devices for accelerating 3D, multimedia, and network processing, including the first PC accelerator from startup ArtX, Mitsubishi's second-generation VolumePro, Fujitsu's FR500, Sun's new MAJC processor, and a radical new chip from startup Cradle Technologies
• Processors for workstations and servers, including details on Intel's Merced, IBM's dual-CPU Power4, simultaneous multithreading technology for future Alpha processors, the highly-parallel SPARC V, and AMD's first Athlon processor for workstations and servers
• Microprocessors for PCs, including Intel's performance enhancements in Intel's Coppermine, Rise's Socket 370 processor, and the next-generation PowerPC chip
• Panel discussions on PC system architecture, server system architecture, and the future of microprocessor design

In addition, there are six one-day seminars presented by Microprocessor Report's analysts:

• Processors for PCs: A Business and Strategy Perspective
• Comparing PC Processor Designs -- Intel's Merced and IA-64: Technology and Market Forecast
• 3D for PCs: Chips, Choices, and Challenges
• Trends in Microprocessors for Embedded Applications
• Processors for DSP: Architectures, Applications, and Vendors

This promises to be the year's premier event for hearing about next year's processors, updating your view of the competitive landscape, and networking with your peers. Don't miss it! Review the full program and register today at http://www.MDRonline.com/mpf/, or call 800.700.4004 or 707.824.4004.

Embedded IC Announcements

S2104 (Applied Micro Circuits): a quad-channel transceiver for high-speed serial data transmission in Fibre Channel applications; each channel operates at 1.062 Gb/s in full-duplex mode. Price: $28/10,000; production: now. Call AMCC at 619.535.4260 or go to http://www.amcc.com/.

24LC01B (Microchip): world's smallest 1K serial EEPROM in a standard package (five-lead SOT-23) retains data for 200 years with one million erase/write cycles; supports I2C protocol; also available in PDIP, TSSOP, and SOIC packages. Price: $0.22/1,000; production: now. Call Microchip at 480.786.7668 or go to http://www.microchip.com/.

RapidSurf BMAX (Integrated Telecom Express): a chipset for ADSL modems with USB; capable of 8-Mb/s downstream and 640 Kb/s upstream links as well as G.lite-standard connections (1.5 Mb/s downstream, 512 Kb/s upstream). Price: $50/1,000; samples: 3Q99; production: 3Q99. Call ITeX at 408.980.8689 or go to http://www.itexinc.com/.