Embedded Processor Watch

Editor: Tom Halfhill

In This Issue:

• IDT Expands Embedded MIPS Family
• Mips Adds a New Dimension to MIPS64
• Industry Resources: Designing Systems-on-a-Chip...
• Industry Resources: ...and Marketing Systems-on-a-Chip
• Embedded IC Announcements

IDT Expands Embedded MIPS Family

Broadening its range of 64-bit embedded processors, IDT is sampling two new MIPS-compatible chips based on the high-performance RC5000 core. The new RC64574 and '575 extend that core in many of the same ways that IDT's RC64474 and '475 extended the 64-bit RC4700 core last year (see Embedded Processor Watch #15, http://www.MDRonline.com/q/epw/issues/epw_15.html).

Improvements over the RC5000 include lower power consumption, a higher clock rate, a simplified bus, cache locking, a JTAG interface, better support for SDRAM, additional instructions for digital-signal processing, and smaller packages with fewer pins. One tradeoff, however, is that the new processors lack a secondary-cache interface, so they'll probably deliver less performance in some applications than an RC5000, even at higher clock frequencies.--T.R.H. (The full version of this article appeared in the August 23 issue of Microprocessor Report.)

Mips Adds a New Dimension to MIPS64

Yet another company is retrofitting a CPU architecture with new instructions for 3D graphics -- this time, even before the first chip based on the architecture comes out. Mips Technologies has introduced MIPS-3D, a set of 13 instructions for MIPS64 embedded processors. MIPS-3D takes advantage of the existing "paired-single" instructions by adding new instructions for matrix multiplication, image clipping, lighting, and other tasks. According to Mips's estimates, MIPS-3D will speed 3D graphics by as much as 83% over the older MIPS-IV architecture. At 500 MHz, a MIPS-3D should be able to draw 10 million polygons per second with lighting, or 25 million polygons without lighting.--T.R.H. (The full version of this article appeared in the August 23 issue of Microprocessor Report.)

Industry Resources: Designing Systems-on-a-Chip...

Check out the latest technology for highly integrated devices at the IEEE's International ASIC/SOC Conference. The show, to be held September 15-18 in Rochester (New York), will be keynoted by LSI Logic CEO Wilf Corrigan and features more than 50 papers on interconnect modeling, logic design, physical design, mixed-signal design, low-power design, verification, and applications. Saturday's schedule includes six half-day seminars providing more in-depth looks at these topics. Registration fees are $480 for the conference and $180 for the seminar day. Discounts are available for IEEE members and for students. For more information, call 301.527.0900 or access http://asic.union.edu/.

Industry Resources: ...and Marketing Systems-on-a-Chip

A new report from Miller Freeman covers the system-on-a-chip market in more detail. The IP 99 Market Report projects future intellectual property (IP) usage by type and extent, analyzes supply channels and IP licensing models, and describes design and verification techniques for highly integrated devices. This information will be helpful whether you are a developer or consumer of chip-level IP. Copies of the report are available for $1,500 (945 pounds sterling) from Miller Freeman UK. For more information or to order, phone 44.0.171.861.6368 or go to http://www.ip99.com/.

Embedded IC Announcements

PACE P2048 (VLSI): a high-density controller for wide-area-network applications that can interface with up to 84 T1 channels for 135 Mb/s of full-duplex aggregate throughput; includes a PCI 2.1 and Utopia Level 2 interface. Price: $240/10,000; samples: now; production: 3Q99. Call VLSI at 800.438.2973 or go to http://www.vlsi.com/.

TLFD500 (Texas Instruments): a codec for G.lite ADSL applications that has a 14-bit converter, 3.3-V I/O, and that interfaces gluelessly to TI's TMS320C54x and TMS320C6x DSPs; offered in an 80-pin TQFP. Price: $9.50/100,000; production: now. Call TI at 800.477.8924 x4500 or go to http://www.ti.com/.