Embedded Processor Watch

Editor: Tom Halfhill

In This Issue:

• MAJC Gives VLIW a New Twist
• Industry Resources: Wear Your Hard Drive On Your Sleeve
• Industry Resources: Embedded News at Microprocessor Forum
• Embedded IC Announcements

MAJC Gives VLIW a New Twist

(Editor's note: This is an analysis of Sun's new Microprocessor Architecture for Java, known as MAJC. For background, see Embedded Processor Watch #62, http://www.MDRonline.com/q/epw/issues/epw_62.html.)

Like other third-generation instruction sets, Sun's MAJC relies on the compiler to handle the instruction grouping and branch prediction done in hardware by traditional processors. MAJC adds variations to this theme that make it uniquely qualified for a range of embedded applications. In contrast, most other modern VLIW architectures are designed for specialized algorithms, and IA-64 is aimed at high-end workstations and servers.

The new instruction set contains many interesting features. A semiabsolute branch-target address improves a critical timing path in the instruction cache. A "prepare to jump" instruction enables zero-overhead branching by prefetching instructions from the branch target. Nonfaulting loads can be hoisted above branches to cover cache delays. A variety of special instructions, such as parallel integer arithmetic, dot product, pixel distance, byte shuffle, count leading zeroes, and population count, accelerate multimedia and cryptography algorithms.

To reduce code expansion, a bane of most VLIW instruction sets, MAJC uses a 32-bit instruction word. This requires some compromises in the capabilities of the instructions, but it reduces code size. MAJC uses a simpler register file than IA-64 and avoids the complexity of full predication, instead substituting a few conditional instructions. With these simplifications, MAJC may not deliver the same performance as IA-64 on some applications, but it should be a strong performer, outrunning traditional processors in many cases.

MAJC's biggest performance advantages will be in graphics, signal-processing, and executing Java bytecodes. The instruction set includes fast thread switching, array-index checking, and support for just-in-time (JIT) compilers. MAJC is not as well suited to applications that demand minimum cost or minimum power; in these cases, architectures such as ARM or SuperH are likely to be a better fit. In applications such as set-top boxes, cellular base stations, and digital cameras, where performance is important, MAJC should fare well.--Linley Gwennap (The full version of this article appeared in the September 13 issue of Microprocessor Report.)

Industry Resources: Wear Your Hard Drive On Your Sleeve

If clipping a cell phone, a pager, and a Palm computer to your belt doesn't make you feel enough like Batman, pretty soon you'll be able to wear a full-blown PC, too. The future of wearable computing is explored in a fascinating white paper available for free on the Web. It's the result of a study conducted by the Institute for Complex Engineered Systems at Carnegie Mellon University in Pittsburgh. The researchers drew upon their backgrounds in anthropology and industrial design to study spaces on the human body where solid and flexible forms can rest without obstructing free motion. To download the paper in Adobe Acrobat (PDF) format, go to http://panopticon.edrc.cmu.edu/design/wearability/front.html.

Industry Resources: Embedded News at Microprocessor Forum

There's only one more week until the 12th annual Microprocessor Forum, October 4-8, at the Fairmont Hotel in San Jose. The two-day conference will include the first disclosures of more than 15 microprocessors, including new embedded chips and cores from IBM, Hitachi, STMicroelectronics, Mips Technologies, and National Semiconductor.

IBM will announce a new embedded PowerPC processor with very high performance; Hitachi and ST will describe their jointly designed 64-bit SH-5 architecture; Mips will reveal its first MIPS64 core; and National will disclose more details about its Geode SC1400 "information appliance on a chip." Other companies will describe new DSPs, 3D-graphics accelerators, and media processors.

For those interested in PC processors, Intel will reveal the microarchitecture of Merced, its first IA-64 processor, and RISC vendors will disclose the new processors and techniques they will use to distinguish their offerings. In addition, the seminar program includes six seminars on embedded processors, PC processors, IA-64, 3D graphics, and DSPs. For more information and to register, go to http://www.MDRonline.com/q/mpf/ or call 800.700.4004 or 707.824.4004.

Embedded IC Announcements

PIC18Cxxx (Microchip): a four-member family of eight-bit RISC microcontrollers that can execute up to 10 MIPS at 40 MHz. They have up to 16K of 16-bit one-time-programmable memory and 1.5KB of user RAM. Other features include five- to eight-channel ten-bit A/D converters, programmable low-voltage resets, and programmable brownout detection. Price: $5.98/10,000; production: now. Call Microchip at 480.786.7668 or go to http://www.microchip.com/.

AD9852/54 (Analog Devices): direct-digital synthesizers that can synthesize a DC to 120-MHz analog sine wave. The AD9852 has a 12-bit, 300-MHz D/A converter, and the AD9854 has dual 12-bit DACs. Prices: $15.40 to $22.50/1,000; production: now. Call ADI at 800.262.5643 or go to http://www.analog.com/dds/.

RTC8563 (Epson Electronics): a real-time clock module that achieves Y2K compliance by extending the two-digit year to four digits with the addition of a century counter. It has a built-in 32.768-KHz crystal and transmits address and data over a two-line bidirectional I2C bus. Price: $2.50; production: now. Call Epson at 310.955.5300 or go to http://www.eea.epson.com/.