Embedded Processor Watch

Editor: Tom Halfhill

In This Issue:

• Sun Makes MAJC With Mirrors
• Industry Resources: Get Portable in San Diego
• Industry Resources: Cool Products at Winter CES
• Embedded IC Announcements

Sun Makes MAJC With Mirrors

At last month's Microprocessor Forum, chief architect Marc Tremblay of Sun described the first implementation of the new MAJC architecture (see Embedded Processor Watch #62, http://www.MDRonline.com/q/epw/issues/epw_62.html, and Embedded Processor Watch #67, http://www.MDRonline.com/q/epw/issues/epw_67.html). With two identical and independent but cooperative processor cores, the MAJC-5200 is one of the first microprocessors to implement chip multiprocessing (CMP), though Sun prefers to classify the chip as a multiprocessor system on a chip (MPSOC). It will offer a relatively high clock rate (500 MHz), eight powerful function units, a unique geometry decompression engine, and copious amounts of off-chip data bandwidth. Future MAJC processors could incorporate hundreds of cores on the same die.

Sun plans to tape out the MAJC-5200 by early December and begin sampling chips in the second quarter of next year. At 200 mm^2 in a 0.22-micron six-layer-copper process, the chip will not be an inexpensive embedded controller, but it could offer an excellent price-performance ratio. Sun says more than one internal customer is ready and waiting. A later version of the chip, known for now as the MAJC-5200+, will have a much smaller die. While still not small enough to be an inexpensive embedded controller, the MAJC-5200+ should be appropriate for a much broader range of products.

Given the game of leapfrog in CPU performance claims, the raw speed of the MAJC-5200 is impressive. At 500 MHz it achieves 6.2 GFLOPS for single-precision data, 1.5 GFLOPS for double-precision data, 7 GOPS for 32-bit integer data, and 13 GOPS for 16-bit integer data. The MAJC-5200 can execute up to six operations per cycle from a grab bag of bit extract, byte shuffle, shift, move/pick conditional, convert, and compare instructions, which yields 3 GOPS for these operations. For the standard bcopy loop (a useful primitive Unix function), the chip achieves 1 GByte/s.

As with any new architecture, however, MAJC faces a steep uphill climb: it won't be easy to generate enough profit to sustain the architecture's costly development. Fortunately, Sun has hitched MAJC to a couple of sturdy new performance bandwagons -- chip multiprocessing and speculative method execution -- and the MAJC-5200 has proved, at least in simulations, that these techniques are one way to keep improving the performance of single-threaded applications.--Brian Case (The full version of this article appeared in the October 25 issue of Microprocessor Report.)

Industry Resources: Get Portable in San Diego

If you design cell phones, notebook computers, or other mobile equipment, check out Portable Design 2000. The show, to be held next January 24-27 at the San Diego Coronado Island Marriott, focuses on the challenges of designing low-power, compact devices. The first day of the conference features a management track, followed by three days covering technical issues, including microprocessors, DSPs, displays, analog circuits, and packaging.

Early (before 11/14) registration costs $650 for the four-day conference or $450 for the first day (management track). For information or to register, contact Nuala Kimball at PennWell (Nashua, N.H.) at 603.891.9267 or on the Web at http://www.portable-design.com.

Industry Resources: Cool Products at Winter CES

Check out the coolest new products for home and work at 2000 International CES, scheduled for next January 6-9 in Las Vegas. The show will feature high-tech products for home networking, 1394 interconnectivity, DVD, digital imaging, digital radio, smart cards, speech technology, and more. Bill Gates, Scott McNealy, and Eric Benhamou will deliver keynote talks. More than 1,500 companies will exhibit their wares at this massive show. Register by 11/12 for free entry to the show floor. To register, go to http://www.CESweb.org/.

Embedded IC Announcements

EPF10K30E (Altera): a 30,000-gate FLEX 10K programmable-logic device (PLD) with PLL, 24,576 bits of embedded dual-port RAM, 1,728 logic elements, and 2.5-V operation. It also supports 64-bit 66-MHz PCI. Price: $20/25,000 and up; production: now. Call Altera at 408.544.7000 or go to http://www.altera.com.

EP20K60E (Altera): an APEX PLD with multiple PLLs, 2,560 logic elements, 32,768 bits of RAM, the ability to function as content-addressable memory (CAM), and PCI compliance (64 bit, 66 MHz). Price: $15/25,000 and up; production: 2Q00. Call Altera at 408.544.7000 or go to http://www.altera.com/.

EP20K1500E (Altera): an APEX PLD with four PLLs, 54,720 logic elements, 466,944 bits of RAM, the ability to function as content-addressable memory (CAM), and PCI compliance (64 bit, 66 MHz). Price: factory-specified per customer (for comparison purposes, the lower-density EP20K1000E starts at $450/10,000); production: 2Q00. Call Altera at 408.544.7000 or go to http://www.altera.com/.