Embedded Processor Watch

Editor: Tom Halfhill

In This Issue:

• Transmeta Unveils Crusoe Chips
• HP and ST Collaborate on VLIW
• Cahners MicroDesign Resources Annual Awards
• Cahners MicroDesign Resources Seeks New Analysts

Transmeta Unveils Crusoe Chips

After nearly five years of unprecedented secrecy, Transmeta (http://www.transmeta.com/) has revealed a new approach to x86 CPU design -- VLIW chips that it claims are part hardware and part software.

Transmeta achieves x86 compatibility by emulating the x86 architecture with hardware-assisted software. The technology is similar to the x86 emulators sold by Insignia Solutions and Connectix for the Macintosh, and it also has much in common with the Java just-in-time (JIT) compilers built into popular Web browsers. The hardware features built into Transmeta's Crusoe chips reduce the overhead of emulation, but there's still some penalty, so the 400- and 700-MHz clock speeds of the processors cannot be directly compared to the frequencies of other x86-compatible chips.

Even so, Transmeta has created two processors with some attractive characteristics. According to company founder Dave Ditzel, the power dissipation of the Crusoe chips is typically around one watt -- much less than any current mobile x86 processor from Intel, AMD, VIA, or Rise. Although Transmeta did not disclose definitive performance benchmarks, it claimed that the high-end 700-MHz TM5400 Crusoe chip will deliver roughly the performance of a Pentium III-500 on PC applications.

Transmeta's lower-end TM3120 Crusoe chip peaks at 400 MHz with similar power-consumption characteristics. It's intended for non-PC information appliances and other embedded applications. Transmeta has created a specially compacted version of Linux that's optimized for "Webpads" and similar devices. If Transmeta's power ratings are close to accurate, the company may capture a significant number of sockets in today's thin-and-light notebooks and tomorrow's Web-enabled embedded appliances.--K.D. (The full version of this article is available to Microprocessor Report subscribers on the Web at http://www.mdronline.com/mpr/h/2000/0124/140405.html)

HP and ST Collaborate on VLIW

Hewlett-Packard Labs and STMicroelectronics have jointly developed a new customizable VLIW embedded-processor technology that will debut later this year. The technology allows developers to rapidly create application-specific VLIW processors with compatible development tools, simulators, and RTOS kernels.

HP and ST embarked on the project in 1997 with the goal of bringing the high instruction-level parallelism (ILP) of VLIW to embedded processors. By itself, that's not a unique idea. In the past year, new embedded VLIW architectures have been announced by Sun (see Embedded Processor Watch #62, http://www.mdronline.com/epw/issues/epw_62.html) and Fujitsu (see Embedded Processor Watch #60, http://www.mdronline.com/epw/issues/epw_60.html). High-performance DSPs from Analog Devices, StarCore, and Texas Instruments use VLIW too. And the ability to customize a core for specific applications is the main selling point of ARC Cores and Tensilica, which allow customers to reconfigure and extend their basic RISC cores (see Embedded Processor Watch #52, http://www.mdronline.com/epw/issues/epw_52.html and Embedded Processor Watch #35, http://www.mdronline.com/epw/issues/epw_35.html). What sets the HP/ST project apart is that it brings developer-driven configurability to a high-performance VLIW architecture for the first time.

Starting with a basic architecture, embedded-system developers can create application-specific instructions to speed critical routines and algorithms, and they can vary the number of function units and registers in the core. Using automated tools, HP and ST generate a CPU simulator that allows developers to test and refine their custom architecture. When the performance is satisfactory, HP and ST generate a processor core that meets the customer's specifications, stripping away unneeded instructions and other features that would inflate the die size and waste power. Finally, HP and ST use automated tools to generate a compiler, assembler, linker, debugger, and RTOS kernel that's compatible with the custom architecture.--T.R.H. (The full version of this article is available to Microprocessor Report subscribers on the Web at http://www.mdronline.com/mpr/h/2000/0124/140403.html)

Cahners MicroDesign Resources Annual Awards

On January 27, Cahners MicroDesign Resources (which publishes Embedded Processor Watch and Microprocessor Report) will announce its 1999 Analyst's Choice Awards and present two new, full-day seminars.

During a special dinner program, "Processing the Future 2000," Cahners MDR will present the First Annual Microprocessor Report Technology Forecasts and Analyst's Choice Awards. The evening program will include forecasts by Microprocessor Report analysts of significant microprocessor technology trends, innovations and challenges for the year ahead, and a special awards presentation celebrating the companies and products that shaped the electronics industry in 1999.

The prestigious Analyst's Choice Awards are given in five categories recognizing excellence in semiconductor technology innovation, design and implementation. Categories, finalists, and winners are:

TECHNOLOGY AWARD 2000 NOMINEES

Compaq Alpha 21464

HAL SPARC64 V

Hewlett-Packard/Intel IA-64

IBM POWER4

Sony/Toshiba Emotion Engine and Graphics Synthesizer

Sun MAJC

WINNER: To be announced on January 27

BEST EMBEDDED PROCESSOR NOMINEES

ARC Cores V3 configurable core

C-Port C-5 network processor

IBM PowerPC 405GP

Intel/Level One IXP1200 network processor

Motorola DSP56690

Sony/Toshiba Emotion Engine

Tensilica XTensa configurable core

WINNER: Sony/Toshiba Emotion Engine

BEST PC PROCESSOR NOMINEES

AMD Athlon

Intel Coppermine

Motorola PowerPC G4

WINNER: AMD Athlon

BEST SERVER/WORKSTATION PROCESSOR NOMINEES

Compaq Alpha 21264

HP PA-8500

IBM POWER3

Intel Pentium III Xeon

WINNER: Intel Pentium III Xeon

BEST 3D ACCELERATOR NOMINEES

3dfx Voodoo 3

ATI Rage Fury MAXX

Matrox G400

Nvidia GeForce 256

WINNER: Nvidia GeForce 256

The new seminars are "The Intel Microprocessor Forecast: The Challenges for the Future" (presented by Microprocessor Report Editor-in-Chief Keith Diefendorff and Senior Analyst Kevin Krewell) and "Extreme Processing: New Architectures for Multimedia and Networking" (presented by Senior Analyst Peter N. Glaskowsky).

Both seminars will be presented on January 27 at the Westin Hotel in Santa Clara, California. Online registration is available at the MDR web site with each seminar priced at $795. The complete package of one full-day seminar plus "Processing the Future 2000" is priced at $845. Cost to attend the dinner event only is $99. Companies can also reserve tables for 10 for $990.

For more information, visit the MDR web site at http://www.mdronline.com/now/MPRawards1 or call 408.328.3900.

Cahners MicroDesign Resources Seeks New Analysts

Cahners MicroDesign Resources, the publisher of this newsletter as well as Microprocessor Watch and Microprocessor Report, and the organizer of Microprocessor Forum and Embedded Processor Forum, is seeking new analysts to join its team. Positions focused on either embedded processors or PC processors are available. Our analysts are highly visible thought leaders in the microprocessor industry and frequently meet with top architects and executives. Candidates must have at least five years of relevant design, marketing, or analysis experience as well as excellent communication skills. For more information, contact Michael Slater (mailto:mslater@mdr.cahners.com).