Embedded Processor Watch

Editor: Tom Halfhill

In This Issue:

• JAZiO: Slow Edges Can Run Fast
• Motorola's Symphony Plays Digital Music
• Industry Resources: Game Developers Conference
• Transmeta, PC Processors, and IA-64 at March 9 Event

JAZiO: Slow Edges Can Run Fast
By Kevin Krewell

JAZiO promises the ability to transfer very high-speed digital data with slower edge-rate signals than was possible before and with noise margins comparable to true differential signals. JAZiO's answer to fast bus design changes the ground rules by not judging a logic state purely in the voltage domain on a fixed clock edge. Instead, JAZiO determines the data by detecting a change, or the absence of a change, from the preceding state over a full bit time. Differential signaling of the interface design allows better noise margins at lower voltage swings.

The JAZiO bus would typically be composed of up to 18 data lines and two complementary control signals: VTR (voltage-time reference) and VTR#. The VTR signals provide both a reference voltage and a clock (actually a bit time reference) for the data signals as each data line is compared simultaneously with both true and complement VTR lines. In order to achieve differential sensing, each data signal uses dual comparators to compare the data signal with both VTR signals. Since the two VTR signals are complementary, it follows that one of them is the complement of the data -- the comparator with the greater difference is used to supply the internal data bit. A bit time is defined as the period that the VTR signal transitions from one level to the other (high-to-low or low-to-high). In effect, if you consider VTR as a clocking signal, it allows data to be transferred on both "edges" of VTR.

One of the beauties of JAZiO technology is that it's applicable to a wide range of interfaces, including buses for memory, processors, backplanes, communications, and graphics. It can also be used for internal chip buses. The JAZiO team filed for a number of patents and is offering the technology under conventional patent licensing terms. For more information see the JAZiO Web site at http://www.Jazio.com/. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0221/140802.html).

Motorola's Symphony Plays Digital Music
By Tom R. Halfhill

Motorola's latest DSP -- the DSP56366 Symphony -- has enough performance and on-chip memory to handle a wide variety of digital-audio standards, and it's aimed at the lucrative market for next-generation consumer-audio products.

Sampling this quarter and scheduled for volume production in 2Q00, Symphony is a 24-bit fixed-point DSP that's compatible with Motorola's DSP56300 family. Motorola plans to deliver 100- and 120-MHz versions of the part, which has 69K of RAM and 240K of ROM on chip. Such a generous helping of on-chip memory allows Symphony to support many digital-audio standards with little or no external RAM.

The DSP is fast enough to process the data streams for all major audio standards, including Dolby Digital AC-3, DTS, MP3, MPEG-2, THX, HDCD (high-definition compatible digital), AAC (advanced audio coding, an enhancement of MPEG-2), and MLP (meridian lossless packing, an audio-compression standard for DVD). (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0131/140506.html).

Industry Resources: Game Developers Conference

There will be plenty of fun at the Game Developers Conference (March 8-12 at the San Jose Convention Center), but don't let that distract you from the other necessities of life -- or the valuable information in the tutorials and six tracks of conference sessions. Registration fees vary from $150 to $1,575. More information is available online at http://www.gdconf.com/.

For an executive-level view of the industry, try the Game Executive Conference (March 7-8 at the Monterey Convention Center). Registration fees are $1,300 to $1,900 and include admission to the Game Developers Conference. For more information, see http://www.gameexecutive.com/.

Transmeta, PC Processors, and IA-64 at March 9 Event

Microprocessor Report's next quarterly seminars and dinner meeting, to be held March 9 at the Westin Santa Clara, will feature seminars on PC processors and IA-64, as well as a dinner presentation by Transmeta CEO Dave Ditzel.

This dinner presentation provides a rare opportunity to hear directly from Transmeta's founder about the design tradeoffs in the Crusoe design, the innovations in the VLIW architecture and code morphing software, and how it may affect the future of the microprocessor industry.

Two seminars are offered concurrently. "Inside Today's PC Processors: Architectures, Microarchitectures, and Performance" will be presented by Keith Diefendorff, editor in chief of Microprocessor Report. This seminar gives an inside look at the microarchitectures, bus and cache architectures, and performance of the most important PC processors. This is our most technical seminar and is designed for attendees who want to understand the internal design differences in today's PC processors.

The second seminar, "Intel's Itanium and IA-64: Dawn of a New Era?," will be presented by Linley Gwennap, founder and principal analyst of The Linley Group. This seminar starts with the philosophy behind IA-64's EPIC technology and then moves into a description and evaluation of the complete instruction set. Linley explains the Itanium design, compares it with its RISC and x86 rivals, and projects the performance and pricing of Itanium -- as well as future IA-64 processors such as McKinley, Madison, and Deerfield.

Registration is $99 for the dinner presentation only, $795 for a seminar only, or $845 for one seminar and the dinner meeting. Register today on the Web at http://www.MDRonline.com/sve or call 800.527.0288. Advance registration is required.