Embedded Processor Watch

Senior Editor: Tom Halfhill
Contributor to this issue: Peter N. Glaskowsky, Senior Editor

In This Issue:

• JSTAR Coprocessor Accelerates Java
• NEC Decants Merlot Media Processor
• Tidbits: Tiny TCP/IP Stack Runs On 8/16-Bit Chips
• Tidbits: NEC's Latest Automotive Controller Supports FCAN
• Industry Resources: Embedded Processor Forum June 12-16
• Cahners MicroDesign Resources Seeks New Analysts

JSTAR Coprocessor Accelerates Java

By Tom R. Halfhill

While bytecode-native Java chips continue struggling to find a market, a team led by former Sun engineers has invented a novel alternative: a coprocessor that attaches to any CPU core and translates Java bytecodes into native instructions on the fly. The coprocessor is available now as a licensable Verilog model from JEDI Technologies, a Santa Clara-based startup founded in 1998.

JEDI's 32-bit coprocessor, called JSTAR, is architecture neutral. Programmable microcode and a bus-interface wrapper allow it to work with almost any 32- or 64-bit microprocessor -- RISC, CISC, VLIW, embedded, desktop, or server. It requires no modifications to the host CPU core, operating system, or application software. CPU and ASIC designers can integrate JSTAR on a chip without altering the processor's I/O interfaces or pin compatibility.

JSTAR is compact and versatile. At 30,000 gates, it occupies only about 1mm^2 of die area in a typical 0.18-micron IC process. It can run at the host processor's core frequency, so its performance will scale on a linear curve with the CPU's native performance. When wedded to a 1.5V RISC core at 180MHz, its logic circuits consume about 18mW and its SRAM (for microcode storage) typically needs another 15mW. It's compatible with existing cache hierarchies, memory interfaces, and MMUs. It steps out of the way during native-code execution, and it doesn't interfere with Java native methods.

Initially, JEDI is focusing on the embedded market. That's a logical strategy, because JSTAR allows a microprocessor to run Java programs much faster than a bytecode interpreter without the memory required for a just-in-time (JIT) compiler. Over time, JEDI hopes that JSTAR coprocessors will become as commonplace in microprocessors as FPUs, which also made their first appearance as auxiliary coprocessors. We think JSTAR is less compelling outside the embedded market, however. Larger systems can more easily spare the CPU cycles and memory required by JIT compilers, adaptive compilers, statically compiled Java programs, and other software-based solutions that improve Java performance even more than JSTAR does. Still, that leaves a huge market for JSTAR. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0327/141304.html).

NEC Decants Merlot Media Processor

By Peter N. Glaskowsky

NEC's new MP98 is a single-chip four-way multiprocessor for multimedia applications based on a new architecture, a control-flow model NEC dubs FOPE, for fork-once parallel execution. In the FOPE model, a thread has exactly one opportunity to issue an explicit fork, enabling parallel execution of multiple instances of the thread. For example, the first time through a loop, a thread may fork off a second instance to handle the second iteration of the loop. NEC says this model greatly reduces the complexity of the control-flow circuitry compared with more general execution models, allowing a complete hardware solution in a relatively simple device.

The MP98 is a 125MHz media processor with four processor cores, a large shared register file, a 64K instruction cache, and an eight-bank 64K data cache. Each of the four cores can issue two instructions per clock, allowing NEC to claim a peak execution rate of 1 GOPS (billion operations per second) on 32-bit data. For 16-bit multiply-accumulate operations, the chip's throughput is 3 GOPS.

Though NEC has not described any plans to produce this chip or use it in specific applications, the new design appears to be competitive in overall complexity, performance, and power consumption with commercial media processors such as Fujitsu's FR-V. With 14 million transistors in a 0.15-micron process, the 110mm^2 MP98 should be reasonably affordable to manufacture. Performance should be more than adequate for consumer-electronics products such as DVD players, also one of Fujitsu's target markets. If NEC decides to put this new architecture into production, we would expect to see the first chips later this year or early in 2001. For more information, visit NEC's Web site at http://www.labs.nec.co.jp/MP98/. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0320/141201.html).

Tidbits: Tiny TCP/IP Stack Runs On 8/16-Bit Chips

CMX Systems has released CMX-MicroNet, a new TCP/IP stack that's compact enough to fit into 1.8K-11K of ROM and run natively on 8- and 16-bit processors. CMX claims CMX-MicroNet is an order of magnitude smaller than any other commercially available TCP/IP stack. It runs alone or on an RTOS and supports TCP, PPP, UDP, SLIP, IP, and HTTP protocols over direct or dial-up connections. Currently it runs natively on 8051 and Atmel AVR-series eight-bit processors, and on Hitachi 300H, Infineon 80C16x, Mitsubishi M16C, and Philips XA-series 16-bit processors. --T.R.H.

Tidbits: NEC's Latest Automotive Controller Supports FCAN

NEC has announced the V850/SF1, a 32-bit microcontroller with an integrated FCAN (full control area network) controller on chip. The V850/SF1 is designed for advanced automotive applications, such as cockpit entertainment systems, but it's also suitable for factory automation and other embedded applications. Sampling begins in May. For more information: http://www.nec-global.com/. --T.R.H.

Industry Resources: Embedded Processor Forum June 12-16

Registration is now open for the Embedded Processor Forum, which will be held June 12-16 at the Fairmont Hotel in San Jose. Vendors will introduce more than 20 new embedded processors, and analysts will present six full-day technical seminars. Embedded Processor Forum will give you the in-depth technical information you need to make winning embedded-design decisions. Due to high demand, we expect registration to fill up quickly. To get more detailed information about the forum and registration, visit the Cahners MicroDesign Resources web site at http://www.MDRonline.com/EPF or call 800.527.0288 or 408.328.3900.

Cahners MicroDesign Resources Seeks New Analysts

Cahners MicroDesign Resources, the publisher of this newsletter as well as Microprocessor Watch and Microprocessor Report, and the organizer of Microprocessor Forum and Embedded Processor Forum, is seeking new analysts to join its team. Positions focused on either embedded processors or PC processors are available. Our analysts are highly visible thought leaders in the microprocessor industry and frequently meet with top architects and executives. Candidates must have at least five years of relevant design, marketing, or analysis experience as well as excellent communication skills. For more information, contact Keith Diefendorff (mailto:kdiefendorff@mdr.cahners.com).