Embedded Processor Watch

Senior Editor: Tom Halfhill
Contributor to this issue: Steven H. Leibson, Chief Embedded Analyst

Jazz Joins VLIW Juggernaut

By Steven H. Leibson

Improv Systems has rolled out its Jazz PSA (programmable system architecture) platform, a design system based on a chip-multiprocessing metacore. Each individual Jazz processor is a configurable VLIW processor with a two-stage pipeline, a variable-width (depending on configuration) VLIW instruction word, and a small, configurable amount of instruction memory.

Jazz PSA is a system architecture that comprises a mix of heterogeneously configured Jazz processors (called task engines), on-chip data and instruction memory, I/O modules, and a global bus called the QBus for on-chip task and control communications among processors. Where the best superscalar RISC and VLIW processors are now executing around 4 instructions per cycle, Improv claims that the Jazz PSA achieves 8 to 12 instructions per cycle per processor.

The Jazz PSA connects individual task engines, using multiple shared data-memory blocks in an architecture well suited to systolic processing (a common approach to processing media streams). Task engines employ shared memory blocks to pass processed data between processor pairs.

Improv selected a somewhat unlikely system-definition language for its Notation Environment, the embedded application development system that's part of the Jazz PSA platform. It chose Java as a structured system-development environment for Jazz PSA. Although there are very credible efforts under way to make Java an effective real-time programming language, none of Java's liabilities as an embedded development language come into play with Improv's Jazz PSA. Improv circumvented the problems with Java by using only the language's syntax. Nothing under the hood of Improv's Notation Environment resembles the JVM or any other existing Java environment.

System developers describing systems based on the Jazz PSA don't use Java directly as a programming language. Instead, Java's syntax is used within the Notation Environment to describe system-level behavior, creating what Improv calls a directed control dataflow network or DCDN. After creating and debugging an application design with the Notation Environment, Improv's Solo Compilation Environment reduces the design to a set of software blocks and a specific implementation of the Jazz PSA.

Solo performs an initial analysis of the Java-based application description; breaks the application into individual tasks; schedules tasks and assigns them to specific task engines; compiles the tasks into VLIW instruction streams for the various task engines in the target implementation; and then analyzes the performance of the resulting hardware/software system. The results of this second analysis provide information for tuning the configuration of each task engine. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0327/141303.html).

MIPS Joins Forces With TSMC

By Tom R. Halfhill

MIPS Technologies has formed a partnership with TSMC (Taiwan Semiconductor Manufacturing Co.) to make prehardened versions of its soft embedded-processor cores. Among other things, the deal gives customers the option of paying a design-use fee instead of the higher cost of a MIPS architectural license while saving the time and trouble of porting a soft core to an IC process themselves. Initially, TSMC will manufacture a hardened version of the MIPS32 4Kc in a 0.18-micron process. It's scheduled to be available in 3Q00. In 4Q00 or 1Q01, TSMC will manufacture a hardened version of the MIPS64 20Kc, a 64-bit core that MIPS will officially announce at Embedded Processor Forum in June. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0403/141411.html).

Tidbits: Lexra Raises $7.5 Million

Lexra has raised $7.5 million in second-round financing, which will come in handy as the company continues developing new cores for the embedded-processor market. The company is also fighting a patent-infringement lawsuit by MIPS Technologies over its MIPS-like cores (see Embedded Processor Watch #78, http://www.MDRonline.com/epw/issues/epw_78.html). Founded in 1997 and based in Waltham, Mass., Lexra offers processor cores that are largely compatible with the MIPS architecture. For more information: http://www.lexra.com/.

Tidbits: LSI Logic Licenses MoSys Memory

LSI Logic has licensed 1T-SRAM memory technology from MoSys for use in future ASICs and ASSPs (application-specific standard products). The addition of 1T-SRAM to LSI's CoreWare library will allow chip designers to integrate several megabits of SRAM with a processor core, using standard logic processes -- unlike embedded DRAM, which requires a more specialized IC process (see Embedded Processor Watch #38, http://www.MDRonline.com/epw/issues/epw_38.html). For more information: http://www.lsilogic.com/.

Embedded Processor Forum: June 12-16

Registration is now open for the Embedded Processor Forum, which will be held June 12-16 at the Fairmont Hotel in San Jose. Vendors will introduce more than 20 new embedded processors, and analysts will present six full-day technical seminars. Embedded Processor Forum will give you the in-depth technical information you need to make winning embedded-design decisions. Due to high demand, we expect registration to fill up quickly. To get more detailed information about the forum and registration, visit the Cahners MicroDesign Resources web site at http://www.MDRonline.com/EPF or call 800.527.0288 or 408.328.3900.

Cahners MicroDesign Resources Seeks New Analysts

Cahners MicroDesign Resources, the publisher of this newsletter as well as Microprocessor Watch and Microprocessor Report, and the organizer of Microprocessor Forum and Embedded Processor Forum, is seeking new analysts to join its team. Positions focused on either embedded processors or PC processors are available. Our analysts are highly visible thought leaders in the microprocessor industry and frequently meet with top architects and executives. Candidates must have at least five years of relevant design, marketing, or analysis experience as well as excellent communication skills. For more information, contact Keith Diefendorff (mailto:kdiefendorff@mdr.cahners.com).