Embedded Processor Watch

Senior Editor: Tom Halfhill

In This Issue:

• Lexra Introduces LX4189 Core
• Massana Teams With Lexra, Xemics
• Sneak Preview: Embedded Processor Forum
• Patriot Scientific Allies With ProSyst

Lexra Introduces LX4189 Core

By Tom R. Halfhill

Lexra has introduced its fifth MIPS-like embedded-processor core, the LX4189. It's very similar to the 32-bit LX4180 core rolled out a year ago, except that it has an additional pipeline stage to reach higher clock frequencies. Lexra says the LX4189 is better suited for next-generation 0.15-micron fabrication processes.

While the older LX4180 has a conventional MIPS five-stage pipeline, the new LX4189 adds an extra stage at the front of the pipe for accessing instruction memory. Besides shortening a critical path and boosting clock speeds, the deeper pipeline also makes it easier for ASIC designers to work with the synthesizable model of the core, because clock timings are less critical.

According to Lexra, the LX4189's worst-case clock frequency in a typical 0.15-micron process is 266MHz, and the core will occupy only 1mm^2 of die area. In comparison, MIPS Technologies specifies a worst-case clock frequency of 200MHz and a nominal frequency of 280MHz for a five-stage MIPS32 4K-series core in a larger 0.18-micron process, with the core occupying 1.4mm^2. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0508/141906.html).

Massana Teams With Lexra, Xemics

By Tom R. Halfhill

Silicon Valley startup Massana has formed partnerships with two providers of embedded-processor cores -- Lexra and Xemics -- to offer integrated cores that combine CPUs with Massana's DSPs. The new solutions span the range from very low power applications to medium-performance applications and are available for licensing now.

Massana's deal with Lexra teams the FILU-200 soft DSP (see Embedded Processor Watch #71, http://www.MDRonline.com/epw/issues/epw_71.html) with Lexra's LX4180, a 32-bit soft CPU core that's largely compatible with the MIPS instruction set (see Embedded Processor Watch #30, http://www.MDRonline.com/epw/issues/epw_30.html). The integrated solution is designed for system-on-a-chip (SOC) devices aimed at broadband communications and networking applications.

The deal with Xemics, a Swiss company, combines a lower-end version of Massana's DSP (the FILU-50) with a proprietary 8-bit RISC microcontroller core (CoolRISC). The FILU-50/CoolRISC is designed for low-power embedded applications, such as motor-control modules, sensors, Internet-enabled mobile appliances, medical devices, and personal communicators. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0508/141905.html).

Sneak Preview: Embedded Processor Forum

By Tom R. Halfhill

More than 20 companies will reveal new microprocessors, processor cores, DSPs, and other technologies during the conference sessions at Embedded Processor Forum, June 13-14. Here's a sneak preview:

* High-Performance Processors For Embedded Systems (Tuesday, June 13)

MIPS64 20K (MIPS Technologies): The first public disclosure of the latest MIPS64-compatible processor core will describe the 64-bit superscalar R20Kc, which delivers 1,000 Dhrystone mips and 2 GFLOPS. MIPS will also disclose its new MGB-Link I/O interconnect scheme that provides 3GB/s of peak bandwidth.

SB-1 (SiByte): Startup SiByte, founded by former engineers from Digital Semiconductor, will reveal the first details of its new superscalar MIPS64-compatible processor core designed for high-performance communications applications.

PowerPC 7xx (IBM Microelectronics): The newest member of IBM's PowerPC 700 family is a superscalar processor with an FPU and integrated L2 cache for very high performance.

DVine SM2700 (Silicon Magic): The SM2700 is the first standard product based on the DVine (DRAM Vector engine) chip-multiprocessor architecture. It combines on-chip DRAM with multiple 32-bit RISC cores and a 16-channel vector processor, all connected to memory-interface units by multiple 128-bit buses.

TriCore V1.3 (Infineon): A future TriCore device will use chip multiprocessing and will be the first implementation of the new Version 1.3 architecture. Features include a high-speed local memory bus, a coprocessor bus, and enhanced multicore debug support.

IMJAZZ-HW5-09 (Improv Systems): This will be the formal introduction of a five-processor implementation of Improv's configurable data-path VLIW architecture. It has multiple VLIW DSP engines, on-chip SRAM and ROM, and programmable I/O components.

* Low-Power and High-Integration Embedded Processors (Tuesday, June 13)

A Low-Power MIPS32 Core (Alchemy Semiconductor): Startup Alchemy, founded by former StrongARM engineers, will disclose a new MIPS32-compatible core that runs faster than 500MHz and consumes as little as 200mW.

Crusoe (Transmeta): Here's a closer look at the innovative LongRun power-management technology that allows Transmeta's x86-compatible Crusoe processors to dynamically scale their voltage and clock frequency to conserve power based on real-time performance needs. Transmeta will demonstrate LongRun and disclose new technical details.

TMS320C55x (Texas Instruments): TI will explain some innovative approaches to power management that allow the latest 'C55x DSPs to consume only one-sixth as much power as current 'C54x DSPs while boosting performance.

aJ-100 (aJile Systems): This is the formal introduction of aJile's aJ-100 integrated processor, which natively executes Java bytecodes while achieving real-time response and low power consumption. The aJ-100 is a multithreaded Java core with on-chip memory and I/O devices.

Maverick 9213 (Cirrus Logic): This ARM920T-based processor integrates numerous peripherals and power-management features to provide an embedded solution for digital-audio applications, such as MP3 players. Cirrus will disclose previously unrevealed details about the 9213.

* Embedded Processor Performance and Profiling (Tuesday, June 13)

The EDN Embedded Microprocessor Benchmark Consortium (EEMBC) will announce new benchmark results and explain the essential functions of its benchmark tests. (Presented by Markus Levy, president of EEMBC.)

* Cool, Lame, & Weird Embedded Apps (Tuesday, June 13)

Steve Leibson, chief embedded analyst for MicroDesign Resources, will take a humorous look at some of the more unusual applications for embedded processors.

* Communications Processors (Wednesday, June 14)

CS2000 (Chameleon Systems): The first public disclosure of a network processor that contains a 32-bit control processor, fixed-function peripherals, and a heterogeneous switched fabric of reconfigurable field-programmable logic elements capable of executing 24 BOPS.

Manta (BOPS): The first chip based on the ManArray DSP architecture has a 2x2 array of processing clusters, each of which consists of four processing elements, each with an integer unit and FPU. It delivers 24 BOPS and 1.3 GFLOPS.

Monadnock (Lexra): The first public disclosure of a new RISC processor core with architectural enhancements for packet processing. It permits the easy design of chip multiprocessors, allowing it to accommodate OC-192 data rates.

Fast Pattern Processor (Agere): The first public disclosure of a processor that can recognize and classify millions of packets per second without the need for content-addressable memory or segmentation-and-reassembly (SAR) devices. The first chip in this family can process 6 million packets per second, and future chips will process 50 million packets per second.

* IP Alternatives for Embedded System Design (Wednesday, June 14)

CPU Plug-Ins (ARC Cores): The first public disclosure of a microprocessor core that works with third-party plug-ins. ARC's new technology will allow developers and IP providers to create customized instruction sets, register files, and bus configurations for vertical-market applications.

T1025 (Tensilica): New extensions to the Tensilica Instruction Extension (TIE) language will allow developers to define new data types and create associated memory-access, arithmetic, field-manipulation, and Boolean instructions for Tensilica's configurable processor core. Tensilica will also disclose the first chips designed with the enhanced TIE language.

High-Speed I/O (JAZiO): This startup company will explain its new licensable I/O technology for embedded-system design.

PowerPC 440GP (IBM Microelectronics): IBM will disclose the first highly integrated embedded processor based on the PowerPC 440 core announced at last year's Embedded Processor Forum. The 440GP has a 128-bit CoreConnect bus and 18 integrated peripherals, including a memory controller, PCI bridge, and Ethernet controller.

* MEMS: Advances in Microelectromechanical Silicon for Embedded Design (Wednesday, June 14)

Roger Grace, principal of Roger Grace Associates, will deliver a detailed presentation on an entirely new class of silicon-based products that provide sensors and actuators for embedded systems.

* DSPs for Embedded Systems (Wednesday, June 14)

C6401 (Texas Instruments): TI will disclose technical details about the first DSP based on the TMS320C64x core, which boosts DSP performance by 10x. The presentation includes new details about TI's memory subsystem and high-speed peripherals.

Multicore Architecture for 3G Mobile (Motorola): This will be the first in-depth look at Motorola's architecture for third-generation wireless products -- an architecture that combines the StarCore SC140 DSP with the M-Core 340 microcontroller.

Carmel 2000 (Infineon): The first detailed disclosure of the second-generation Carmel DSP architecture will include benchmark results documenting a 2x increase in performance.

* Information Appliances: Challenges and Opportunities (Wednesday, June 14)

MDR founder and principal analyst Michael Slater will lead this special panel discussion with participants from InfoGear, PictureIQ, Cirrus Logic, S3, and Microsoft.

For more information about Embedded Processor Forum, visit the Cahners MicroDesign Resources web site at http://www.MDRonline.com/EPF. You may also call 800.527.0288 or 408.328.3900 for more information or to request a brochure.

Patriot Scientific Allies With ProSyst

Patriot Scientific has formed an alliance with ProSyst USA to port the latter's mBedded server software to Patriot's PSC1000 processor family (see Embedded Processor Watch #44, http://www.MDRonline.com/epw/issues/epw_44.html). This will allow the bytecode-native PSC1000 to run embedded Java applications with networking capabilities. ProSyst's mBedded software is compatible with the wireless application protocol (WAP), Microsoft's Universal Plug and Play, and Sun's Jini (see Embedded Processor Watch #42, http://www.MDRonline.com/epw/issues/epw_42.html). Patriot and ProSyst are targeting mobile devices such as PDAs, smart cell phones, Java smartcards, office equipment, and home appliances. For more information: http://www.ptsc.com and http://www.prosyst.com. --T.R.H.