Processor Watch

February 14, 2005

Editor: Tom R. Halfhill

In this issue:

Cell Moves Into the Limelight
Kevin Krewell - Senior Editor  {02/14/2005}

Cell is real. Cell is out—finally! IBM has been eager to reveal more about a project on which it has been hard at work for almost five years. The Cell processor has been shrouded in secrecy, necessitated by the competitive nature of the multibillion-dollar game-console market. With the first production units still at least a year away, Sony, Toshiba, and IBM now feel comfortable to begin revealing the nature of the processor and the system design.

The Cell processor is technically a family of processors compliant to the specifications of the Broadband Processor Architecture (BPA), the new architecture designed to process media data. Future implementations could have differing numbers of Power and Synergistic Processor cores. The Cell processor has one Power core and eight Synergistic Processor cores.

BPA (Cell) design features include the following:
· Extension of the Power Architecture
· Coherent and cooperative off-load processing
· Enhanced 128-bit SIMD architecture
· Power efficiency improved over that of conventional architectures
· Linux port derived from work on PowerPC
· Resource allocation management
· Locking caches (via replacement management tables)
· Multiple memory page table sizes
· Isolation mechanism for secure code execution

Fundamentally, the Cell processor consists of three main units supported by two Rambus interfaces. There is a single Power architecture processor that acts as the main host processor, eight single-instruction, multiple-datastream (SIMD) processors, and a highly programmable DMA controller.

Even though the ISSCC presentations talk about 4.6GHz operation, don’t expect the final product to run at that speed. Cell will be used in Sony’s next-generation gaming console and in Toshiba TVs. Those products are expected in 2006.

Microprocessor Report readers can access the full story (9 pages; 7 graphics) here: www.mdronline.com/mpr/h/2005/0214/190701.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Are Instruction Sets Irrelevant?
Kevin Krewell - Senior Editor  {02/14/2005}

This article is based on a series of conversations with Scott Sellers, vice president of hardware engineering, CTO, and cofounder of Azul Systems, and represents Sellers’ opinions. Further analysis of Azul Systems’ performance will require greater access to the final product.

Azul is a startup company building a new multiprocessing server architecture that the company refers to as a compute appliance. Azul is betting on the trend that more corporate application development is using IBM WebSphere, JBoss, BEA WebLogic, etc., with J2EE-based platforms replacing the venerable Cobol, C, and C++ programming languages. Azul points to a Gartner report from September 2004 that shows that about 50% of new enterprise software is being developed in virtual machine environments like Java and .NET and will account for 80% of enterprise software development in 2008.

The unique thing about Azul’s compute appliances is that they are designed to offload Java (and other virtual machine-based environment) processing loads from traditional servers. Azul’s appliances run the virtual machine environment on a separate network-attached server added to a data center without disturbing existing systems. To build this system, Azul initially looked to traditional (off-the-shelf) microprocessors to power its compute appliance architecture, but none offered the right combination of 64-bit performance, multicore scaling, and system reliability features that Azul needed. In addition, Azul needed an instruction set that could easily be extended to support the company’s unique approach to virtual machine management. The result is that the company built its own custom processor designed specifically for virtual machine operation. Still, the details of the Azul processor are not what is important about the system—what is important is the software machine built on top of the processors.

Building the compute engine led Sellers’ team to conclude that if the next generation of corporate software were to be based on virtual machine software—be it Java, Microsoft’s .NET, Python, or a proprietary design like SAP’s ABAP platform—the underlying computer ISA would become irrelevant once the virtual machine architecture were ported. The ISA is no longer the point of compatibility; it is the language construct itself. This form of virtualization removes the processor hardware from the compatibility equation. The important design issue is designing a processor and a system architecture that efficiently execute a virtual machine software architecture.

Azul Systems is currently in field trials of its compute appliance with major IT customers and plans to announce pricing and availability later this year.

Microprocessor Report readers can access the full story (4 pages; 2 graphics) here: www.mdronline.com/mpr/h/2005/0214/190702.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

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