Processor Watch

December 27, 2004

Editor: Tom R. Halfhill

In this issue:

Bringing Power to the People
Kevin Krewell - Senior Editor  {12/27/2004}

IBM is leading an effort to build an open consortium around the Power Architecture. The consortium is going under the name Power.org, which is also its web address. IBM gathered 15 companies, many existing partners plus some new partners, to put this program together to build an open-standards community around chips and systems that use the Power Architecture.

According to the press release: “Power.org’s members intend to define open specifications related to Power Architecture technology with two initial focus areas: bus architecture and high volume servers.” The group’s activity will center on IBM’s Power Architecture. The instruction set and intellectual property cores will continue to be licensed and controlled by IBM.

The companies coming together to form the Power.org community are AMCC, Bull, Cadence Design Systems, Chartered Semiconductor Manufacturing, Culturecom, IBM, Jabil Circuit, Novell, Red Hat, Sony Corporation, Shanghai Belling, Synopsys, Thales, Tundra Semiconductor, and Wistron. Some of the names are familiar; others are less well known. Culturecom is a Linux software provider (as are Novell and Red Hat). Shanghai Belling, founded in 1988 by Shanghai Electronics & Instruments Holding Co. Ltd. and Shanghai Bell Telephone Manufacturing Co., is a joint venture of Alcatel Bell and was the first semiconductor manufacturing joint venture in mainland China—and is one of the largest. The other foundry listed is IBM process-development partner Chartered.

Key details of the organization must still be hammered out by the board members in 1Q05, so much work remains. The Power Architecture is one of the premier processor architectures in the world. IBM hopes to make it one of the most popular as well.

Microprocessor Report readers can access the full story (2 pages) here: www.mdronline.com/mpr/h/2004/1227/185202.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Editorial: 2004 in Review
Kevin Krewell - Senior Editor  {12/27/2004}

As we close out 2004, it’s a time to look at the year, assessing the progress we’ve made and the work still ahead. At In-Stat/MDR, we established our first international forum, and we look forward to the second annual Processor Forum Taiwan in the fall of 2005. With the goal of offering increased value for your subscription in 2004, we emphasized deeper-content stories with more analysis, running fewer short, newsy stories. We are planning our 2005 editorial calendar to schedule certain in-depth stories over the year. We will be adding new features, like a buzzword and codename glossary, and the ability for readers to provide quick feedback on content.

Our goal in 2005 is to bring more industry input to the direction of the newsletter. To obtain more high-level feedback, we are creating an industry advisory council, to which we are inviting technology leaders in key companies. Our goal for the council is to set up a panel of people that can help direct us to the best content and technology trends for Microprocessor Report and for the forums. We will announce the first council members in January.

The Rise of the Multicore Processor

In the industry, 2004 was clearly the year of the multicore processor. It’s not that we didn’t have dual-core processors in servers before (IBM’s Power 4), or in high-performance embedded processing (SiByte/Broadcom and PMC-Sierra), but in 2004, Intel staked its desktop and notebook roadmaps to multicore processors. After Intel’s missteps with the Tejas cancellation, revised 4GHz introduction, and 90nm processor shipment delays, the company very publicly embraced multicore, for all its product lines, as the new path to increased performance. Still needed is more client application software that is multithreaded-aware and can scale single-application performance with additional cores. Modern server software is largely ready for multithreaded, multicore processors, but client software, with a few exceptions (like Adobe Photoshop), still has a way to go to use multiprocessor architectures efficiently. Intel did have a head start with Hyper-Threading technology, but there is more work to be done.

In many ways, however, Intel’s designs are not very adventurous. The first dual-core desktop processor consists of two Prescott cores on a single die, with little redesign. The first real ground-up, dual-core design is the 65nm Yonah design for notebook computers. We don’t know anything about that design yet, but it is not expect to ship until 2006 in systems. AMD’s dual core Opteron, while more elegant with its shared on-die memory controller interface, is also a straight-forward design.

The most aggressive designs for multicore, multithreaded processing in 2005 will come from companies other than AMD and Intel. In servers, Sun Microsystems’ Niagara processor has stripped the core down to the basics in order to pack the die with eight quad-threaded cores. First silicon is working, and Sun has publicly stated it will ship systems with Niagara in early 2006. Vendors at the high end of the embedded processor space are also moving to more cores, such as Cavium’s Octeon processor with up to sixteen MIPS64 cores; Broadcom with four MIPS64 cores (for real this time) on one die (BCM14xx); and Freescale with the first dual-core PowerPC processor (PowerPC 8641D).

Another very exciting architecture on the horizon is the IBM/Sony/Toshiba Cell architecture. Although the initial focus of the design is Sony’s next-generation console machine, the Cell architecture is being touted as having applicability in devices ranging from handhelds to supercomputers. That is quite a tall order for one architecture. No architecture has succeeded over such a broad range of applications, not even the ubiquitous x86. Cell may be over-hyped right now, but the concepts behind it are not so radical as to be incomprehensible. Cell also fits nicely into the movement toward parallel processing, but it includes additional programming-management controls over the parallelism.

The End of an Era

The company that popularized the PC for business, created an industry, and (along the way) made Intel and Microsoft very, very rich, is now spinning off its PC division. IBM announced it is spinning off its PC division to a joint venture with Chinese computer company Levono. The new company will also be called Levono, but it will be able to use the IBM brand name for five years. It will take the IBM PC group fully intact.

The financial analyst community applauded the move and has also called for HP to spin off its own PC division as well. Once the darling of the technology market, PCs are now often considered commodity products, having little differentiation and slim margins. IBM’s ThinkPad line of notebooks is widely recognized as the cream of the crop, and its recently revamped line of corporate desktops contains systems that are smaller and value priced, but they still didn’t provide the company with enough value to keep.

The new Levono will be mostly a pure PC company, a rare occurrence in an era where the hot products are consumer devices. In China, however, the existing Levono makes other items, such as cellphones and servers. Once the deal is completed, in 2Q05, the new company may decide to expand beyond PCs and export those other items outside China.

So, must we now call the PC combination of an x86 processor and Microsoft software a “Levono-compatible PC”?

Reader Feedback

As always, we look for feedback from our readers. I would like to encourage you to drop us a note with your feedback on the articles we covered during the past year. What was your favorite, or what was the most outstanding? Which made the most difference to your job? What is your suggestion for articles in 2005?

Next month we will be naming our 2004 Analyst Choice Awards, always a popular topic. We’re skipping the dinner this year and will announce the winners in the newsletter in January.

From all of us at Microprocessor Report, I’d like to wish you a healthy and prosperous New Year.

M2000’s Spherical FPGA Cores
Max Baron - Principal Analyst  {12/27/2004}

The best indicator of a lucrative market is the wide spectrum of product introductions aimed at solving its problems. For the embedded world, the multiple offerings of instruction- set architecture (ISA) extension and configuration speak louder than words; their hopeful creators seek to secure a slice of the revenue promised by combining vanilla CPUs with special-purpose instructions. In many cases, adding special instructions and the hardware to execute them is perceived to be simpler and less costly than introducing a complex hard-wired finite-state machine (FSM) or a second programmable processor employing a better-targeted instruction set.

With most of the semiconductor vendors that matter offering proprietary and/or customer-generated instruction-set enhancements, the race is on for the best implementation solution, with the usual contradictory requirements of best performance, cost, power, flexibility, and time to market. After a rather long gestation period, starting in 1996, M2000, a 15-employee French company, is introducing a new FPGA architecture in cores it is licensing under the name FlexEOS. (The name bears no connection to an operating system; it combines Flex with EOS, the mythological Greek winged goddess of the dawn.)

Microprocessor Report readers can access the full story (5 pages; 4 graphics) here: www.mdronline.com/mpr/h/2004/1227/185202.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

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