Microprocessor Watch

Editor: Michael Slater
Contributors: Linley Gwennap, Keith Diefendorff, Peter Glaskowsky

In This Issue:

• IA-64 Instruction Set Revealed
• Cyrix Reworks Roadmap
• SiS Defends Turf Against Intel's 810
• TSMC Wins 0.18-Micron Foundry Race
• Industry Resources: Microprocessor Report Seminars and AMD K7 Dinner Meeting presentation, **June 10**
• Industry Resources: Platform99

IA-64 Instruction Set Revealed

Intel and HP have released a full description of the IA-64 application-level instruction set architecture (see http://www.hp.com/go/ia64), allowing a full evaluation of the new ISA. The instruction set itself is straightforward and not too different from other RISC-like instruction sets with multimedia extensions. IA-64's uniqueness lies in its extended capabilities: a large register file, predication, speculation, and a newly disclosed feature called register frames. Register frames are similar to SPARC's register windows but are dynamically sized by the ALLOC instruction, providing much greater flexibility and efficient use of the 128 integer registers. Several subroutines can coexist within the register file without saving registers on the stack, reducing subroutine call overhead. When the register file is full, the processor automatically spills values to memory, providing software with the illusion of an infinite register file.

All IA-64 processors will provide full x86 compatibility (for more details, see http://developer.intel.com/design/ia64/devinfo.htm), but the overhead for calling an x86 routine is much greater. The x86 registers are mapped onto IA-64 registers, and most IA-64 registers must be saved to memory before switching modes. Thus, mode switching is likely to be done only at a high level, such as when calling an x86 application from an IA-64 operating system.

IA-64 provides the compiler with an unprecedented amount of control over the hardware. The biggest challenge for HP and Intel is to deliver compilers that can take advantage of this control to deliver strong performance. If these compilers can at least match the performance of RISC compilers, IA-64 should be successful in the workstation and server markets.

The May 31, 1999 issue of Microprocessor Report includes a full description of the instruction set. Cahners MicroDesign Resources' newly revised report, "Intel's Merced and IA-64: Technology and Market Forecast" (see http://www.MDRonline.com/tl/ia64 for ordering information), provides an in-depth analysis of IA-64's technology and market prospects.

Cyrix Reworks Roadmap

Just a few weeks after National announced its intent to get out of the PC processor business, Cyrix unveiled major changes to its roadmap. At the heart of the changes is the decision not to pursue the PC market with integrated processors but instead to stick with processors that follow Intels interfaces and integration level.

The first chip due to roll out under the new strategy, code-named Gobi, combines the Cayenne core (an enhanced derivative of the M II), a 256K on-chip L2 cache, and a Socket 370 interface. The on- chip L2 cache should provide a significant speed boost, and the CPU core enhancements significantly improve MMX and floating-point performance--two weak points of the M II.

Cyrix has dropped its plan for the chip code-named Jedi, which was to be a Socket 7 version of Gobi. It also indefinitely delayed the MXi, which was to be an integrated processor based on the Cayenne core, and shelved the previously planned M3 (see MPR 11/16/98, p. 24). Instead, the roadmap now shows Mojave, which uses the Jalapeno core but follows the Intel-standard Socket 370 interface.

When, or even if, Gobi or Mojave sees the light of day depends on how quickly Cyrix is sold, what the buyers plans are, and how difficult the transition is. The new chips could put the product line on a more competitive footing, if they could be delivered on time and at sufficient clock speeds.

SiS Defends Turf Against Intel's 810

Silicon Integrated Systems (SiS) has introduced single-chip PC core-logic products meant to compete more directly with Intel's 810 chip set (see MPR 5/10/99, p. 17) than previous SiS integrated-graphics products such as the 530 and 620 (see MPR 9/14/98, p. 4). These older SiS chip sets are widely used in low- end PCs today, and their successors should be even more popular. The improved 540 and 630 chips (for Super Socket 7 and P6-bus systems respectively) feature a 128-bit 3D accelerator and a local-area network controller compatible with the 1-Mbit/s Home Phoneline Network Alliance (http://www.homepna.org) and 10/100- Mbit/s Ethernet standards. The 540 and 630 are priced at $35 in quantity and will be available this summer. For more information, visit the SiS Web site: http://www.sis.com.tw.

TSMC Wins 0.18-Micron Foundry Race

Taiwanese semiconductor maker TSMC (http://www.tsmc.com) has announced production availability of its 0.18-micron six-layer- metal CMOS process. With CL018, TSMC jumps into the lead as the first foundry to enter production with a true 0.18-micron process. According to TSMC, the new process is 100% more dense, 30% faster, and offers 65% lower power than its current 0.25-micron process. In the third quarter, TSMC will replace the upper two layers of aluminum with copper, improving performance another 15%. The timely availability of such a state-of-the-art process--on a par with those of the traditional microprocessor vendors--could have a dramatic ramifications for fabless semiconductor companies.

Industry Resources: Microprocessor Report Seminars on Intel, PC Processors on June 10

On Thursday, June 10, Microprocessor Report's analysts will present two day-long seminars: choose our deepest technology seminar, "Comparing PC Processor Designs," or our unmatched analysis of Intel's business, "The Intel Microprocessor Forecast."

Then stay for the dinner meeting to get an inside look at AMD's groundbreaking K7, presented by its chief architect, Dirk Meyer. The seminars and dinner meeting will be held on June 10 at the Westin Hotel in Santa Clara. Advanced registration is required. The cost is $595 for either seminar, $99 for the dinner meeting, or $645 for either seminar plus dinner. For more details or to register, visit http://www.MDRonline.com/events/sve, or call at 800.527.0288 or 707.824.4001.

Industry Resources: Platform99

The first Platform99 conference, produced by Bert McComas of InQuest Market Research, will be held July 21-22 in San Jose. This event aims to fill in the gaps in the picture painted at WinHEC and Intel Developer Forum with an independent perspective that considers alternative PC platform strategies. Topics include DRAM technologies, bus standards, chip-set architectures, processor strategies, host processing vs. hardware acceleration of 3D geometry, real-time MPEG-2 encoding, 3D sound, and communications. The event will include dozens of focused briefings from major technology vendors and presentations by independent analysts. Registration is $695 before June 14th, and $895 after that date. Register on the web at www.platform99.com or call 408.985.7785.