Microprocessor Watch

Editor: Michael Slater
Contributors: Linley Gwennap, Keith Diefendorff, Peter Glaskowsky

In This Issue:

• 64-Bit Battle Looms at Microprocessor Forum
• Merced Shows Innovative Design
• Power4 Focuses on Memory Bandwidth
• Athlon Is First PC Processor to 700 MHz

64-Bit Battle Looms at Microprocessor Forum

Among the many disclosures at Microprocessor Forum, perhaps the most dramatic were those surrounding the looming battle of the 64-bit architectures. Intel disclosed many details of Merced's microarchitecture, making it somewhat more concrete, but EPIC's critics (i.e., Intel's and HP's competitors) remained unconvinced. IBM described its tour de force effort to go beyond what IA-64 will deliver with Power4, while Compaq's Alpha team described the simultaneous multithreading technique it plans to use in the 21464. The biggest surprise was AMD's announcement that it will deploy a 64-bit extension to the x86 architecture in its next-generation processor, code-named SledgeHammer, which is due in 2001.

This issue of Microprocessor Watch covers the Merced and Power4 disclosures. Future issues will describe AMD's and Compaq's plans, as well as disclosures about Intel's Coppermine, Motorola's enhanced G4 processor, Hal's aggressive SPARC implementation, and more. (Of course, Microprocessor Report subscribers are receiving the full details in our print publication; see http://www.MDRonline.com/mpr for more information.)

Merced Shows Innovative Design

At this week's Microprocessor Forum, Intel unwrapped the Merced microarchitecture, showing how IA-64's EPIC design results in hardware that is both simpler and more powerful than traditional RISC or CISC processors. Gone are the complex instruction reorder buffers and register alias tables found in modern superscalar processors. In their place are more registers, more function units, and more branch predictors. These trade-offs eliminate unneeded complexity while leaving some dynamic structures in the hardware to handle events the compiler can't easily predict.

Merced microarchitecture manager Harsh Sharangpani described Merced as a six-wide machine, fetching and executing two bundles, or six instructions, per cycle at its peak rate. The processor uses a 10-stage pipeline to achieve high clock speeds, although Sharangpani declined to specify the target clock speed. IA-64 features such as predication, speculation, and register rotation are implemented with simple hardware structures. Dynamic structures, such as a decoupled fetch unit, nonblocking caches, and register scoreboarding, avoid pipeline stalls due to level-one cache misses.

The tighter coupling between the compiler and the processor improves hardware efficiency compared with traditional RISC or x86 designs. For example, the compiler has more control over branch prediction, allowing the processor to focus only on those branches that require dynamic prediction. Since all modern compilers perform instruction scheduling, allowing the compiler to communicate that information directly to the processor eliminates redundant scheduling circuitry. Ultimately, IA-64 gives the compiler more flexibility in scheduling instructions, increasing potential performance as well as the compiler's complexity.

Merced is no longer just a paper design. Intel and its system partners are currently validating first silicon, which has booted four operating systems and several key applications. The company says the processor is on track for mid-2000 production, with systems appearing in 2H00.

According to our performance projections, Merced looks like it will be neck-and-neck with the fastest RISC processors on workstation and server benchmarks. This level of performance will be a big step forward for Intel in the workstation and server markets. The combination of strong native performance and full x86 compatibility has won the backing of virtually every significant workstation and server vendor except Sun. We expect these vendors to roll out a variety of Merced systems, starting in 2H00.

Processor vendors such as Compaq (Alpha) and IBM (Power) still have a few tricks up their sleeves, and they aren't giving up in the performance race. To slow the IA-64 juggernaut, these vendors can't just be as good as Intel-they have to be better. That could be tough. Merced looks to be a solid starting point for IA-64, and Intel will keep raising the bar from there. --L.G.

Power4 Focuses on Memory Bandwidth

Not content to wrap sheet metal around Intel microprocessors for its high-end server business, IBM is developing a processor it hopes will fend off the IA-64 juggernaut. IBM's monster 170-million-transistor chip, boasts two >1-GHz five- issue superscalar cores, a triple-level cache hierarchy, a 10- GByte/s main-memory interface, and a 45-GByte/s multiprocessor interface. IBM expects first silicon in 1Q00, and systems in 2H01.

The processors will be built in IBM's most advanced IC process, a 0.18-micron seven-layer-copper silicon-on-insulator process with aggressive channel lengths. Power4 chips, each of which have 5,500 C4 bumps, are packaged in a four-chip glass- ceramic multichip module with 5,200 I/O pads. This eight- processor MCM, which we expect to dissipate a half kilowatt of power, is about 4.5" on a side and requires hundreds of pounds of force to insert onto a motherboard.

With Power4, IBM has taken a completely different approach to server performance than Intel and HP have taken with IA-64. While Intel and HP have focused on a new EPIC instruction-set architecture to exploit single-thread instruction-level parallelism, IBM has focused on exploiting thread-level parallelism with chip multiprocessing and mind-boggling amounts of memory bandwidth. IBM says that the memory system is now--and will always be--the primary limiter of server performance anyway, so it sees little need for a new instruction set.

For this project, IBM has pulled together technology from every corner of the massive company. Based on the strength of the Power4 design and the technology muscle IBM is putting behind it, it may be a long time, if ever, before IA-64 infiltrates the large servers that are at IBM's heart. --K.D.

Athlon Is First PC Processor to 700 MHz

Reluctant to cede its recently acquired performance title to Intel's forthcoming Coppermine, AMD has raised the frequency of Athlon to 700 MHz, becoming the first x86 processor to reach that mark. The accomplishment should worry Intel. While Athlon has hit 700 MHz in a 0.25-micron process, Intel was able to coax Pentium III to only 600 MHz in 0.25 micron. We expect Intel to take the frequency lead with its 0.18-micron 733-MHz Coppermine later this month, but AMD says it will also enter production this year with a 0.18-micron Athlon, possibly regaining the frequency lead. Athlon prices were reduced across the board to make room for the new 700-MHz part. --K.D.