Microprocessor Watch

Editor: Michael Slater
Contributors: Linley Gwennap, Keith Diefendorff, Peter Glaskowsky

Special Seminar Invitation: Michael Slater on PC Processors

NEXT WEEK: Michael Slater, founder of Microprocessor Report and Microprocessor Forum and editor of this newsletter, will present his seminar "Processors for PCs: A Business and Strategy Perspective" on November 4 at the Westin Hotel in Santa Clara. Hear his candid views on Coppermine vs. Athlon; Intel's Celeron strategy; AMD's prospects; VIA's challenges and opportunities; the future of integrated processors; how information appliances will affect the PC market; and much more. For more details or to register, see http://www.MDRonline.com/dm or call 800.700.4004 or 707.824.4004.

In This Issue:

• Coppermine Outruns Athlon
• PowerPC G4 Gains Velocity
• ATI Mobility Moves to 128 Bits

Coppermine Outruns Athlon

Hidden behind the same brand name as its predecessor, Intel's 0.18-micron Pentium III processor adds features and performance optimizations to strengthen its market position. The new chip, code-named Coppermine, was announced Monday in desktop, mobile, and workstation versions at clock speeds of up to 733 MHz. At this speed, the chip delivers better integer performance than any other, including Compaq's Alpha processor and AMD's Athlon.

At the recent Microprocessor Forum, Intel architecture manager Jim Wilson described the new chip's design. Enhancements over the previous Pentium III, known as Katmai, include an on-die 256K level-two (L2) cache, an improved bus interface, and for the mobile segment, a variable voltage and clock-speed feature called SpeedStep. The combination of the faster cache and faster bus boost performance by at least a full speed grade compared with the original Katmai Pentium III, and the 0.18-micron process delivers higher CPU speeds on top of that increase.

Along with boosting clock speed, the 0.18-micron version reduces cost by bringing the die size down to a highly manufacturable 106 mm2, despite the addition of the on-chip cache. This cache eliminates the need for the bulky, expensive module used for Katmai-based Pentium IIIs. The chip's modest die size and integrated cache significantly reduce Intel's manufacturing cost, boosting margins, and will enable Intel to ramp production of the new design in record time.

Another benefit of the 0.18-micron process is lower power. Coppermine enables Pentium III to reach the mobile market for the first time, providing the benefits of both higher clock speeds and the SSE multimedia extensions. Intel today announced mobile versions at speeds up to 500 MHz, and the mobile parts will exceed 700 MHz next year in the higher-power SpeedStep mode. The integrated cache offers the further benefit of reduced footprint for the smallest mobile systems.

Coppermine creates some transition issues for PC makers, namely the switch to a 133-MHz bus and the eventual move from Slot 1 to Socket 370. These issues are exacerbated by the delays that resulted in the awkward timing of Coppermine's introduction. But within six months, these transition issues will ease. Unfortunately, Coppermine does not immediately help either the high-end server or the low-end Celeron segments. These segments should see the benefits of the new design by the middle of next year. --L.G.

PowerPC G4 Gains Velocity

Feeling cautiously optimistic after Apple's resurrection, Motorola is making a major upgrade to the microarchitecture of its MPC7400 with AltiVec (nee G4), which is at the heart of the Macintosh G4 systems that Apple began shipping in September. The two most significant enhancements the new 74xx has over the current G4 include a deeper pipeline to achieve frequencies of more than 700 MHz and an on-chip 256K L2 cache that boosts memory-system performance substantially. New features have also been added for the embedded market and the design is being prepared for fabrication in Motorola's forthcoming 0.18-micron copper HyperMOS-6 (HIP6) process.

To realize an actual performance gain from the longer pipeline, Motorola made a series of enhancements to offset what otherwise would have been a significant loss of IPC (throughput in instructions per cycle). First, it increased the instruction- issue bandwidth and added new execution units to eliminate some structural hazards. Next, it increased the instruction-reorder depth to exploit more instruction-level parallelism (ILP), and the branch predictor was beefed up to reduce stalls on control- flow hazards.

Motorola's simulations show that together these improvements kept the 74xx's IPC on a par with that of the G4, allowing all the frequency gained from the longer pipeline to fall through to real performance gains. Beyond these performance gains, however, Motorola went on to reduce average memory-access time by including an on-chip 256K L2 cache with 22 GB/s of bandwidth (at 700 MHz) and by converting the G4's backside L2 cache into an L3.

Motorola has not yet announced any products or schedules for the new processor, but sources indicate that the new part taped out about two months ago, indicating a production date of mid-2000. If Motorola can deliver and stay within 5%, or at most 10%, of Intel and AMD on frequency, the new part should keep the Apple platform competitive on general-purpose applications and, with AltiVec (which Apple now calls the "Velocity Engine"), well ahead on multimedia applications for most of 2000. --K.D.

ATI Mobility Moves to 128 Bits

ATI's new Rage Mobility128 graphics accelerator is based on a 128-bit rendering engine derived from the company's Rage 128 Pro graphics chip (see MPR 9/14/98, p. 16). The Mobility128's 345- contact BGA houses a graphics chip along with 8M of SGRAM or SDRAM, externally expandable to 16M. The Mobility128 supports essentially all available flat-panel displays, making it suitable for use in both laptops and LCD-equipped desktops.

ATI says its new chip is substantially faster than S3's Savage/MX and /IX (see MPR 8/2/99, p. 4) on standard 2D and 3D industry benchmarks. The Savage/IX is available with up to 16M of in- package SDRAM, however, reducing the board space needed for high- end configurations. ATI asks $55 for the Mobility128, a dollar less than the price of S3's 8M Savage/IX. --P.N.G.