Microprocessor Watch

Editor: Michael Slater
Contributors: Linley Gwennap, Keith Diefendorff, Peter Glaskowsky

In This Issue:

• Hal Makes Sparcs Fly
• SiS Rises to Via Challenge
• AMD Opens Fab 30
• IBM to Ship PowerPC G4s
• Steve Leibson, Kevin Krewell Join MDR

Hal Makes Sparcs Fly

Hal Computer Systems is developing an innovative 1-GHz, out-of- order superscalar processor it calls Sparc64 V, which it hopes to place into Fujitsu GranPower SMP servers by late 2001.

Sparc64 V uses two instruction-level-parallelism enhancing techniques not found in current mainstream microprocessors: a trace cache and superspeculative execution. The processor can issue up to six integer instructions per cycle, delivering more than 70 SPECint95 (base). On floating-point code, the chip can issue up to eight instructions per cycle, two of them floating- point multiply-add instructions, giving a maximum throughput of 4 GFLOPS and a SPECfp95 (base) score of more than 130.

Sparc64 V has its roots in a class of processors called trace processors. In these processors, the instruction-fetch hardware breaks the code stream into segments called traces that follow the predicted flow of control.

Instructions in traces are predecoded, and knowledge about data- dependence relationships and hardware resource requirements is kept with each trace in a trace cache. By performing much of the work of decoding instructions, analyzing data dependencies, and routing instructions to execution units up front, the trace technique takes pressure off the performance-critical front end of the execution pipeline. Keeping the pipeline short--without compromising speed--was a key design goal for Sparc64 V.

Although Hal says it may go after thread-level parallelism in a future chip--like IBM is doing with chip multiprocessing on Power4 and Compaq is doing with simultaneous multithreading on the Alpha 21464--Hal believes that, for this generation, instruction-level parallelism is the way to go, especially for Fujitsu's primary market target of Unix technical servers.

Hal also believes that compatibility is critical to the server market and does not believe that static scheduling--a la IA-64-- is sufficiently better than dynamic scheduling to justify switching to a new instruction set. If correct, and if Hal can really achieve 1-GHz speeds with Sparc64 V, Hal and Fujitsu will be in a good position to make hay in at least the Solaris- compatible server market, and perhaps in the broader server market as well. --K.D.

SiS Rises to Via Challenge

Worried about being left in the dust by rival chip-set supplier Via Technologies and by Intel's fully integrated Timna processor, Silicon Integrated Systems (www.sis.com.tw) has licensed x86 CPU and related intellectual property from Rise Technology (www.rise.com). Seeing that system logic might be subsumed into the processor, SiS reacted by snatching Rise's technology before Via, which recently purchased Cyrix from National and Centaur from IDT, cornered the market on low-end x86 vendors. --K.D.

AMD Opens Fab 30

Thirty years after being founded, AMD has opened its latest state-of-the-art semiconductor manufacturing facility, Fab 30 in Dresden, Germany. AMD says it will begin production of Athlon chips this quarter, with revenue shipments beginning 2Q00. Once complete, the fab investment will total $1.9 billion, and the facility will be able to crank out 5,000 200-mm (8-inch) wafers per week. The new fab will run Motorola's advanced 0.18-micron copper HiP6L process, with which AMD expects to ship 1-GHz Athlons by the end of next year. --K.D.

IBM to Ship PowerPC G4s

In a surprising turn of events, IBM has decided to make G4s for Apple after all. Last year IBM handed the Macintosh market to Motorola when it packed its bags and walked out of Somerset--the companies' joint design center. Although IBM and Motorola are both apparently bound by contract not to comment on the new deal, both companies and Apple seem satisfied. Apple gets two sources and the security of having the world's most experienced vendor of copper microprocessors backing up its primary vendor. IBM gets to sell G4s to Apple, having invested little effort in developing the part. And Motorola, presumably, gets royalties from parts IBM sells. --K.D.

Steve Leibson, Kevin Krewell Join MDR

We are pleased to announce that Steve Leibson has joined the MicroDesign Resources analyst staff to lead our growing embedded efforts.

Steve has an enviable reputation in the high-tech industry as an award-winning journalist and innovator of consumer, industrial, and medical embedded-system products. He has held leadership positions at EDN magazine, Hewlett-Packard, and Cadnetix, and we look forward to his contributions to the MDR team. Steve is a graduate of Case Western Reserve, where he studied lasers, communications, and product development. He can be reached at mailto:sleibson@mdr.cahners.com.

We are also pleased to welcome Kevin Krewell to our analyst team. Kevin will be focusing his attention on PC processors and you'll be reading many stories under his byline in the near future.

Kevin's microprocessor experience spans more than 20 years, including positions with industry leaders AMD, Hazeltine, and Norden Systems Division of United Technologies. His experience in the defense, computer graphics, and semiconductor industries will bring new insights for our readers. Kevin holds a BSEE from Manhattan College and an MBA from Adelphi University. His email address is mailto:kkrewell@mdr.cahners.com.