Microprocessor Watch

Editor: Kevin Krewell, kkrewell@mdr.cahners.com
Contributors: Steve Leibson

In This Issue:

• XScale (StrongARM-2) Muscles In
• Sun Finally Ignites UltraSPARC IIe
• Microprocessor Forum

XScale (StrongARM-2) Muscles In

By Steve Leibson

The latest incarnation of StrongARM, now renamed XScale, is an embedded processor microarchitecture that pushes both the lowest power dissipation (10mW) and highest performance (1,000 Dhrystone 2.1 mips) envelopes of the embedded world. Naturally, you don't get both low power dissipation and extremely high performance at one time. You do get your choice. The low-power characteristics derive from design techniques that are becoming standard in processor design: extensive use of clock gating, circuit tricks, and dynamic voltage and frequency scaling. Improved processing performance stems from a high maximum clock rate (800MHz); an enhanced ARM V5TE instruction set; larger caches; a branch-target buffer that provides dynamic branch prediction; and additional SIMD instruction enhancements.

XScale's designers have added a 40-bit accumulator, which lives in the ARM coprocessor space, and six new SIMD coprocessor instructions that use this accumulator. Intel says it plans to use these SIMD extensions for audio processing and has defined a coprocessing engine with eight accumulators, although implementing just one in this incarnation. Intel has added these instructions through ARM's coprocessor mechanism, but actual implementation is part of the processor core. Intel has thus employed the standard calling mechanism that ARM created to allow licensees to add architectural improvements, while implementing the enhancements in a way that achieves single-cycle performance and also highlights the special nature of Intel's ARM license.

The full version of this article is available online to Microprocessor Report subscribers at: http://www.mdronline.com/mpr/h/2000/0911/143701.html

Sun Finally Ignites UltraSPARC IIe

By Steve Leibson

Announced last year at Embedded Processor Forum, the UltraSPARC IIe is finally ready to rock and roll. The integrated processor incorporates an execution unit based on Sun's SPARC V9 architecture, with a floating-point unit and VIS (visual instruction set) multimedia extensions; independent 16K instruction and data caches; a unified, four-way set-associative 256K L2 cache; a 32-bit 66MHz PCI bus controller; and a PC-100 SDRAM controller with ECC. The UltraSPARC IIe's SDRAM controller can manage four single- or dual-sided buffered or unbuffered SDRAM modules, for a maximum current capacity of 2GB. Power-management capabilities include a software-controlled clock that can operate the core at full, half, or one-sixth speed, with attendant linear power reductions at each drop in clock rate, from 13W at full speed to 2.5W at one-sixth speed. In addition, the memory controller can put the SDRAM into self-refresh mode, placing the processor into what might best be called a daydream state.

The full version of this article is available online to Microprocessor Report subscribers at: http://www.mdronline.com/mpr/h/2000/0911/143702.html

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Microprocessor Forum 2000
The microprocessor industry's most important week of the year

October 9-13, 2000 San Jose Fairmont Hotel San Jose, CA

Microprocessor Forum 2000 Program Highlights: More than 20 first public disclosures of new chips and architectures from AMD, ARC Cores, ARM Ltd., Centaur Technology, Hewlett-Packard, Hitachi, IBM, Improv Systems, Intel, LSI Logic, Micron Technology, Motorola, picoTurbo, Samsung, SiByte, STMicroelectronics, Toshiba, Vulcan ASIC Ltd., Xstream Logic, and ZF Linux Devices.

Six full-day seminars on today's hottest microprocessor applications:

* Information appliances

* Voice and Data Networks

* High-performance embedded

* Multimedia

* DSP and digital audio

And a unique opportunity to network non-stop with the leaders continuing the microprocessor revolution at the industry's premier annual gathering including a special welcome reception sponsored by ARM on Monday, October 9 and the Microprocessor Forum 2000 Expo: Literature and Demonstration Center sponsored by MIPS Technologies on Tuesday, October 10.

Nothing compares to Microprocessor Forum for the comprehensive view it provides of the industry's direction it provides and the quality of the presenters and attendees it attracts. And now's the time to register -- while hotel rooms are available at a preferred rate. For more information on lodging and logistics, on-line registration, and detailed seminar and program information, please visit our web site at http://www.mdronline.com/mpf. Or call 1.800.527.0288. We're looking forward to seeing you in San Jose!