Microprocessor Watch

Issue #114 -- 11/24/2003

Editor: Kevin Krewell  

In this issue:

Fujitsu Makes SPARC See Double
Kevin Krewell - Senior Editor  {11/24/2003}

Following up on the SPARC64 V presentation at Microprocessor Forum 2002, Takumi Maruyama, manager of the E Processor Development at Fujitsu, presented the SPARC64 VI at Microprocessor Forum 2003. Fujitsu will use its 90nm process to fit two cores and 6MB of L2 cache on one die. The dual superscalar out-of-order cores are expected to clock at significantly greater than 2.4GHz.

Although Fujitsu calls the processor a multithreaded processor, it can also be viewed as a chip-level multiprocessor. To scale server system performance, shared memory data and memory latency are still important problems to be solved. Fujitsu’s solution reflects the prevailing thought in the industry: use a multithreaded or multicore processor. Fujitsu chose the multicore approach and combined it with a new system bus based on a mainframe server design.

The SPARC64 VI will be fabricated in Fujitsu’s 90nm process, with 10 layers of copper interconnect, a 40nm gate width, and low-k dielectric. The die dimensions are 19.1mm ´ 20.3mm (388mm2). The dual core and large cache will push the transistor count to 690 million. The die has 360 I/O pins and a core voltage of 1.0V, with the I/O voltage at 1.8V. Fujitsu already has a test version of the chip running at 2GHz. The SPARC64 VI will have a 6MB 12-way cache with a 256-byte line size and enough bandwidth to support the two cores.

Microprocessor Report readers can access the full story here (3 pages, 3 figures): www.mdronline.com/mpr/h/2003/1124/174701.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

What’s Microsoft’s Game?
Peter Glaskowsky - Editor-in-Chief  {11/24/2003}

Microsoft is a software company, but it does more hardware design than many hardware companies do. Microsoft recently made several key announcements related to the second generation of its Xbox videogame console, and these announcements make it clear the company is taking an entirely new approach to creating the new system. Today’s Xbox is much like a standard x86 PC; its components were state of the art when Xbox shipped, but today they’re simple commodities.

The next Xbox—reportedly to be called Xbox Next—will combine graphics technology from ATI with core logic from SiS to replace the integrated-graphics chip set designed by Nvidia for the original Xbox. Neither of the new partners will provide actual chips; Microsoft will use ATI and SiS circuit designs in new custom ASICs.

The processor picture for the new machine is less clear. Microsoft has licensed PowerPC processor technology from IBM for the new Xbox, but no further information has been released. The particular core could be IBM’s PowerPC 970, the PowerPC 440 used in high-end embedded systems, or some unannounced design. It’s even possible Microsoft will use more than one PowerPC core, but the company hasn’t said.

Microsoft also declined to specify whether the selected core will be the only general-purpose processor in the system. Without an x86 processor, maintaining software compatibility with the original Xbox will be more difficult. Microsoft gained in-house emulation technology through its acquisition of Connectix earlier this year, but emulating a 733MHz Pentium III with sufficient reliability to host performance-intensive videogames would require a far more powerful RISC chip—probably at least a 3GHz device. Multiple slower cores would not work.

To solve this problem, Microsoft could add another processor core, an x86 design licensed from AMD, Intel, or VIA. Xbox currently has a programmable graphics core and an audio DSP coprocessor; Microsoft could presumably adopt a more-complex heterogeneous multiprocessing configuration for the next-generation system. There’s no hint of such a strategy from Microsoft, however appealing it may be. Such a multicore design could enable the concurrency needed to use Xbox Next as a digital video recorder or home multimedia gateway.

Integrating processors, core logic, graphics, and peripherals to create an all-new videogame platform is no easy task, no matter how mature the individual cores Microsoft has licensed. To make Xbox Next competitive against Sony’s forthcoming PlayStation 3, Microsoft will need three or four complex chips, totaling several hundred million transistors. A project of this magnitude could keep a large design team busy for years. Microsoft’s deal with IBM could be tied to IBM’s expertise in custom SoC designs, but we don’t know how much of the design work for the new Xbox—if any—could be handled by IBM.
The company’s investment in new Xbox hardware could approach half a billion dollars, and that figure doesn’t include software development or marketing expenses. I don’t know if Nintendo can afford to match this kind of spending. Sega dropped out of the console competition when Microsoft joined; will Nintendo be the next to give up on hardware to focus on game development?

In creating Xbox Next, Microsoft will gain considerable skills and experience in system-on-chip design. Although it’s unlikely the company would offer chips to the merchant market, Microsoft would effectively become a fabless semiconductor company. These skills could allow Microsoft to pursue other markets, where it has previously relied on external design firms. Microsoft may not need to partner with other companies to pursue markets such as set-top boxes and cellphones, where systems are generally sold through service providers rather than at retail. If Microsoft doesn’t need retail-focused OEMs to sell its designs—as it does in the PC and PDA markets—it may choose to cut out the middlemen and boost its profits. Microsoft could be a fearsome competitor for many companies that today are its partners.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Will Microprocessors Become Simpler?
Don Alpert  {11/17/2003}

The history of processor architecture has experienced several cycles in which following the path of conventional wisdom has led to increasingly complex designs until better, simpler solutions emerged. During the years since the 1980s, the simple RISC architectures of that decade have evolved into complex implementations having high-frequency, superscalar, out-of-order speculative execution engines enabled by elaborate branch-prediction schemes and multilevel caches. We believe that the trend toward simpler architectures has again arrived—at least for workloads having high thread-level parallelism (TLP) and poor locality.

Commercial workloads, such as on-line transaction processing (OLTP), have such large working sets that enhanced pipeline techniques, such as superscalar execution, deliver marginal performance improvement. Multithreading is a technique that allows a single processor to overlap memory accesses from independent processes. Several design examples show that simple processors employing multithreading can demonstrate better cost-performance for commercial workloads than do more-complex processors optimized for workstation workloads.

Microprocessor Report readers can access the full story here (3+ pages, 1 figure): www.mdronline.com/mpr/h/2003/1117/174603.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

UltraSPARC IV Mirrors Predecessor
Kevin Krewell - Senior Editor  {11/10/2003}

As part of its Throughput Computing initiative, Sun has started down the path to chip-level multithreading (CMT) with its UltraSPARC IV (US IV), revealed at Microprocessor Forum 2003. Sun’s first US IV consists of two slightly enhanced UltraSPARC III cores that share a systems bus, DRAM memory controller, and off-die L2 cache. Built in the Texas Instruments 130nm process, the dual cores share one large off-die L2 cache, but when Sun migrates the US IV processor to 90nm, the company will add an on-die L2 cache, with the off-die cache becoming a large L3 cache.

Sun’s goal was to increase performance with a multicore approach, initially without significant increases in clock speeds. Sun’s chip-level multithreading could also be called chip multiprocessing The UltraSPARC IV processor should ship in Sun systems in 1H04 with clock speeds of 1.05GHz and 1.2GHz. UltraSPARC V is presently planned for 2006 as a higher-performing single core with dual-threading support.

The even-numbered member of the UltraSPARC family continues a plan to leverage the infrastructure and system bus created in UltraSPARC III. The goal is to provide a stable platform over an extended period of time. The benefit of this continuity is that US IV can be an on-site upgrade to a number of SunFire systems (V480–V1280, 4800–15K). Solaris can support mix of US III and US IV processors. Pricing was not available at the announcement.

Microprocessor Report readers can access the full story here (3 pages, 4 figures): www.mdronline.com/mpr/h/2003/1110/174502.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

MDR Reorganized, Ready for 2004
Peter Glaskowsky - Editor-in-Chief  {11/10/2003}

We’ve made several changes on the MDR side of In-Stat/MDR. Most important, Markus Levy is no longer on our staff. Markus’s primary area of coverage, high-performance embedded processors, will be shared among our other analysts. We thank Markus for his excellent work for us over the years, and we’re sure we’ll be working with him in the future as he continues in his role as president of EEMBC. Markus has joined the Microprocessor Report editorial board, and we hope he will contribute occasional articles to the newsletter.

Kevin Krewell has returned to full-time analyst duties at his request, giving him more time for his work on Microprocessor Report and the Intel Microprocessors service. Assuming the role of general manager for MDR is Frank Dickson, previously senior director of sales and marketing and principal analyst with In-Stat/MDR.

We believe these changes will strengthen our company as we enter 2004. If you have any questions about them, please write to me at png@reedbusiness.com.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

VIA Keeps It Cool, Safe
Kevin Krewell - Senior Editor  {11/03/2003}

Glenn Henry, president and founder of VIA’s Centaur division, was back at Microprocessor Forum 2003 with an update of VIA/Centaur’s processor plans for 2004 and beyond. Along with the normal processor update, Henry revealed details of future VIA processors, with hardware features that will speed data encryption and security. The new VIA processors include a new version of the Nehemiah processor having the Centaur designation C5P. The C5P is based on the C5XL processor introduced in January, but the circuit design has been repacked to reduce the die size from 52mm2 to 47mm2 and to remove about 100,000 transistors. At the same time, the C5P adds new functionality and has more-aggressive clock gating. All this tuning of the design will allow VIA to both increase the clock speed of the processor and lower its power.

The Centaur team is preparing to tape out the 90nm version of the family, called Esther and numbered C5I. Henry’s target for C5I is a minuscule 33mm2. At this point, VIA plans to upgrade the processor bus to the Pentium M (Centrino processor) bus; in the future, it will offer a VIA bus that is not plug compatible with the Pentium M/Pentium 4. The C5I will add an improved branch predictor and SSE2 instruction support and will have a complete hardware implementation of the SHA-1 standard.

The C5P processor is sampling today. The processor will be available in two packages. The standard package for the C3 processor is a 370-pin Pentium III–compatible PGA (35mm ´ 35mm) package. The smaller BGA package (15mm ´ 15mm) is available as part of the Eden platform and should also be available next year in the Antaur platform.

Volume shipments are expected in 1Q04. Prices have not yet been announced.

Microprocessor Report readers can access the full story here (3 pages, 4 figures): www.mdronline.com/mpr/h/2003/1103/174402.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.