Microprocessor Watch

Issue #120 -- 05/31/2004

Editor: Tom R. Halfhill  

In this issue:

Intel’s PC Roadmap Sees Double
Kevin Krewell - Senior Editor  {05/31/2004}

On Friday, May 7, 2004, Intel made an announcement regarding its processors roadmap that caught many in the industry by surprise. In a statement, Intel announced it was canceling two processors (Tejas and Jayhawk) and accelerating a strategy to bring dual-core processors to the mainstream PC markets. Intel made the announcement the week before its semiannual analyst meeting. At that meeting, Intel executives defended the move, claiming the company had hit “the power wall” with traditional clock-speed scaling. The new roadmap will use dual-core processors in all major markets, starting in 2005.

The cancellation of Tejas, and the volume server version Jayhawk, signals the end of Intel’s plans to advance the monocore CPU architecture. All future Intel processor-development plans will be based on multicore designs. It is also the end of the gigahertz clock-speed race with AMD. This dramatic change in direction was not completely unexpected. At the fall 2003 Intel Developer Forum, the company revealed plans for a dual-core Xeon processor, and the company had previously made it clear that Itanium’s future was multicore.

The move to dual-core processors is recognition that Intel was hitting the power wall in trying to maintain frequency scaling. Beyond that, however, performance should be considered a system issue, and clock speed was becoming a poor proxy for performance. System performance takes into account memory bandwidth, cache size, and platform buses (like PCI-Express and Serial ATA). In addition, Intel will have new features, such as Vanderpool technology, that will improve the user experience

The new processor numbers Intel is rolling out work well with dual-core processors. Intel will be able to ship a dual-core Pentium that has a lower clock frequency than a single-core processor has and yet give the dual-core solution a higher processor number based on the additional performance of two cores. To enable performance scaling with additional processor cores, Intel will need to work with software vendors to give programmers the tools and examples of the way to parallelize code.

Microprocessor Report readers can access the full story (4 pages, 4 graphics) here: www.mdronline.com/mpr/h/2004/0531/182202.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Dothan by the Numbers
Kevin Krewell - Senior Editor  {05/24/2004}

Intel’s second 90nm processor finally hit the road in a range of new Pentium M notebooks on May 10, 2004. Originally, we expected production shipments to commence in late 2003. After resolving a design glitch, however, Intel is now ready to deploy the 90nm Dothan processor in volume and is trying to make up for lost time with an accelerated production ramp in 2H04.

The launch of Dothan also launched Intel’s new Processor Number system. The Pentium M processors (Banias architecture) are part of the mobile 700 series. The Dothan processor was launched in three speed grades: 1.7GHz (model 735), 1.8GHz (model 745), and 2.0GHz (model 755). The company probably skipped 1.9GHz because being so close to a nice round number like 2.0 is often unpopular, but the new processor numbers should eliminate that bias. All the processors have 2MB L2 caches and a 400MHz front-side bus (FSB). Later, Intel will launch the rest of the processor-numbering system for mobile processors with the mobile Pentium 4 (NetBurst) architecture as the 500 series and with Celeron processors as the 300 series. Intel’s processor numbers will be supplemented by information on the processor architecture, cache size, clock speed, front-side bus, and “other” Intel technologies.

The Intel Pentium M processor 755 (2GHz) has a list price of $637 in 1,000-unit volumes. The list price for the 1.8GHz Pentium M processor 745 is $423, and the 1.7GHz Pentium M processor 735 lists for $294, also in 1,000-unit volumes.

Microprocessor Report readers can access the full story (1 page) here: www.mdronline.com/mpr/h/2004/0524/182102.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Risk Reduction Faraday Style
Max Baron - Principal Analyst  {05/18/2004}

Most leading vendors of embedded processors tend to keep under wraps, as long as they can, the details that make their chips work, so it is refreshing to see Faraday taking the opposite approach. Its FA626 ARM v4 core, announced a few weeks ago, and the technology on which it is based are communicated in detail to the world at large, not just to the few prospective licensers associated with the huge corporations leading the communications and networking markets.

Faraday’s brainchild is not your usual processor core, which leaves the expense and risk of interfacing, caching, and core-to-core communication to the design engineer. The FA626 goes a few steps further, since it’s being delivered with its own on-chip interconnect, L2 cache, and coherency logic configured to support additional processing resources. As if these functions alone were not enough, the FA626 also exposes the ARM coprocessor interface, to which the company can help designers connect their processor or accelerator of choice.

Faraday’s target market is “maximum SOC-MIPS, ARM popularity,” which implies that the company hopes to use the popularity of the ARM architecture and its available software development tools to go after applications such as network communications and video, today populated by MIPS and PowerPC engines.

Microprocessor Report readers can access the full story (4 pages, 4 graphics) here: www.mdronline.com/mpr/h/2004/0518/182002.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

VIA Embeds Its Security Strategy
Kevin Krewell - Senior Editor  {05/18/2004}

At Embedded Processor Forum 2004, Glenn Henry, founder and president of VIA’s Centaur Division, updated the company’s processor roadmap and announced additional features on the company’s 90nm processor with improved security processing and media processing. The newest version of the 90nm processor will maintain the “Esther” code-name announced at Microprocessor Forum 2003.

The new C5J processor just completed tape-out in a 90nm IBM SOI, low-k dielectric process. The chip will be only 31.7mm2 and has 26.2 million transistors; samples are expected in 4Q04. The die size is a bit smaller than the 33mm2 that Henry projected at MPF03, and the die is smaller than that for any previous Centaur design. With the smaller die size, the C5J should be cost-effective to manufacture, despite using the more expensive IBM process, but costs will depend on the yields of the state-of-the-art IBM process. The new chip will also add Intel’s SSE2 and a full hardware implementation of SSE3 instructions. VIA added SSE3 on the basis of public information Intel released on the new instructions.

In addition to higher clock frequencies, the C5J will also get a performance boost over its 130nm predecessor, Nehemiah/C5P, from a faster front-side bus and a larger L2 cache. The bus is Centaur’s first implementation of the Intel Pentium M bus and will support a 200MHz base clock and quad-pumped data transfers. The L2 cache was doubled from the 64K, 16-way cache on Nehemiah to the 128K, 32-way version on Esther.

Microprocessor Report readers can access the full story (3 pages, 4 graphics) here: www.mdronline.com/mpr/h/2004/0518/182003.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Reconfigurable “Illogic”
Rich Belgard  {05/10/2004}

Having read Tredennick and Shimamoto’s “point” to this “counterpoint,” I am truly amazed at the naïveté these experienced and bright designers have shown. For at least a decade, some people have been predicting that “reconfigurable logic” will supplant the microprocessor. I think the prediction of the death of the microprocessor is unfounded. I think there is a place for reconfigurable logic—and the place is in addition to, or as an extension to, the microprocessor.

The conclusion of “Microprocessor Sunset” is that microprocessors will no longer be capable of handling the new age of applications—according to the authors, untethered systems.

Fittingly, I am writing this counterpoint on a new Intel ULV-Pentium M laptop, somewhere over Kansas. Weighing around three pounds, my laptop says I have about 4.5 hours of battery left. I wouldn’t even want to guess what battery life I’d have if I were running, on the same silicon, not XP Pro but Word under DOS. Oh, and on this particular trip, my Blackberry has been powered-on for the past three days, receiving my email and stock quotes, and still is at 85% battery life. (And yes, the radio is off only for the flight.) I have my trusty cell phone with me, and its battery lasts about a week, if I am circumspect. Each of these untethered devices uses at least one microprocessor.

So, I find it quite strange that “Sunset” suggests I will need to throw out everything I know, and everything our industry knows, and change the entire paradigm to reconfigurable systems.

Microprocessor Report readers can access the full story (3+ pages) here: www.mdronline.com/mpr/h/2004/0510/181901.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

The Only Constant Is Change
Kevin Krewell - Senior Editor  {05/10/2004}

Those of you who have been paying close attention and who read my last editorial must be wondering why I’m writing this one. My last editorial was my supposed swan song at In-Stat/MDR and Microprocessor Report. Well, after almost four months at a startup, I’m back, and I’m editor in chief of Microprocessor Report. My return is a good news/bad news story. The good news (for me at least) is that I’m glad to be back at In-Stat/MDR and writing for Microprocessor Report. It’s also another opportunity to contribute to the microprocessor community in the best way I know how. The bad news is that my return is due to the departure of Peter Glaskowsky. Peter was a long-time and valued contributor to MDR, and he will be missed here.

I consider being Microprocessor Report’s editor in chief a great honor and a great responsibility. I was recently talking to the CEO of a major Silicon Valley chip company and he told me how much he values the in-depth and impartial content of Microprocessor Report and that he reads it on a regular basis, mostly on planes. (In fact, MPR seems to be the reading material of choice for many subscribers on airline trips. Maybe we should publish airline schedules in the report for even greater utility.)

My goal is to make our content even more relevant as the microprocessor industry tackles the challenges of complex system-on-chip (SoC) designs, 90nm and smaller geometries, intellectual property (IP) use and reuse, the rise of untethered computing, and many other issues. This is a very dynamic industry, and MDR must change to continue to be of value to it.

Over the next few months you can expect to see some changes here. But we will not lose our staunch independence and objectivity, although they will not prevent us from getting excited when we find a company or product or technology we think is really significant.

Some of these changes will be seen at the Embedded Processor Forum, which is fast approaching as I write this. Because microprocessors do not work without software, we have an EPF04 session on software technologies that includes an intriguing presentation from Transitive Technology, which claims its software will allow any processor to run instructions from another instruction set.

We also recognize that the embedded market (except for most x86 processors) has moved to SoC designs, and that connecting the various cores on the die is as significant a challenge as designing the cores themselves. At EPF04, on Wednesday afternoon, we have a panel covering on-chip buses, addressing both licensable IP and proprietary solutions. Chip designers must decide where to invest their limited resources in designing interfaces and when they would be better off licensing existing technology. Much like the trade-off SoC designers face with IP cores, the system bus can be licensed, or it can be designed in house. But the system bus is often even more critical, because, as the backbone of the SoC processor, it must connect various IP blocks and, ideally, should be scalable for the future. The panel will be moderated by a new addition to MDR’s staff but a returning veteran of In-Stat, Jim McGregor. Jim brings additional systems expertise to MDR as well as having an established background in research.

I will be opening EPF04 and moderating the Tuesday session on high-performance embedded processors. We will have presentations from ARM, Motorola/Freescale, PMC-Sierra, and VIA. As usual, we have representatives from all the key embedded instruction set architectures and most of the important vendors. I hope to see you there.

I’m very excited to be back at MDR and Microprocessor Report, and I hope I can count on you, our readers, for your continued support. I also hope we can tap into your collective wisdom and knowledge to help make this newsletter an essential part of your business.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Microprocessor Sunset
Nick Tredennick and Brion Shimamoto  {05/03/2004}

Semiconductors have been a great business; the industry has seen the equivalent of 14% growth for the past 40 years. No other industry matches that. The integrated circuit, Moore’s law, and the personal computer were a great beginning. But we’re at the end of the beginning with the value PC, the value transistor, and the decline in semiconductor-process adoption rates.

This article describes how the industry arrived at value PCs and at value transistors, and it discusses the consequences. To put the conclusion up front, the market is shifting from tethered systems (plugged into the wall for power) to untethered systems. As it shifts, the engineering goal is changing from cost-performance to cost-performance-per-watt. However, today’s microprocessors and DSPs cannot satisfy the combined performance and power requirements of untethered systems. ASICs are too expensive. Programmable logic devices are too slow and too expensive. Current memory components—DRAM, SRAM, and flash memory—are unsuitable. Faster transistors burn less active power, but in two process shrinks, their leakage currents rise by an order of magnitude—not a good thing for untethered systems.

In other words, we can’t get there just by shrinking the components we have.

The situation seems to be a problem with no solution, but the industry is about to emerge from a 30-year stall in the improvement of design methods that was caused by our preoccupation with the microprocessor. The solution is reconfigurable systems combined with a new nonvolatile memory cell.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2004/0503/181801.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.