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Intel asserted its technical prowess and squashed concerns about losing market share to its rival by opening the doors to the new Core microarchitecture and the future-product roadmaps at the Spring 2006 Intel Developer Forum (IDF). The result will be an aggressive transition to the Core microarchitecture for all mobile PC, desktop PC, and volume server dual- and quad-core processors within the next 12 months. The transition will begin with the Merom mobile PC, Conroe desktop PC, and Sossaman server processors, beginning in 3Q06.
If off-the-shelf network processors don’t fit the bill, but designing a custom part is too costly or intimidating, Teja Technologies has a fresh alternative: Teja FP (FPGA Platform). It’s a package of development tools, software, and hardware intellectual property (IP) that allows software engineers to build a packet processor in an FPGA without using a hardware description language (HDL) or fabricating custom silicon.
With Teja FP, programmers can start with existing data-plane code written in ANSI C or write new code in that language. After profiling and analyzing the code, the next step is to partition the application. The most compute-intensive parts can execute in the FPGA’s programmable-logic fabric, while other parts can run on soft processor cores synthesized in the fabric. Although, at present, the profiling, analysis, and partitioning are largely manual tasks, Teja FP can automatically compile ANSI C into logic for the hardware partition or into assembly language for the software partition. In addition, Teja offers some prewritten hardware and software IP for accelerating common packet-processing tasks.
Teja FP is primarily intended for optimizing data-plane code at wire speeds in the 1Gb/s to 2Gb/s range. Control-plane code can run on hard processor cores embedded in the FPGA or on an external processor. For now, Teja FP works only with Xilinx Virtex-4 FX devices, so the lone integrated-processor option is the PowerPC 405. Customers preferring an external processor can compile their control code for virtually any CPU architecture.
Because Teja FP targets FPGAs for both development and deployment, it offers several advantages over conventional solutions. Programmers can bend the hardware to match the software, instead of writing software that must conform to the fixed architecture of a standard-part processor. Development is a feedback-driven iterative process, allowing programmers to fine-tune the application’s hardware and software partitions for optimal performance. Deployment is rapid and less risky, because it eliminates the need to spin custom silicon. Upgrades are easier, even in the field, because the software partition is fully programmable, and the hardware partition is implemented in reprogrammable logic. Result: a highly customizable, flexible packet processor.
