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ARM’s Cortex-A8 processor implementation of the ARMv7 architecture employs a 13-stage deep pipe to obtain high-integer performance. The deep-pipe processor can also be scaled back in frequency and voltage to reduce the core’s power consumption to 300mW at 600MHz.
In the Cortex-A8 processor, the ARM core, together with its NEON execution unit, provides the company’s first desktop-function 1.0GHz engine, capable of high performance on integer data, fixed- and floating-point operations, digital-signal processing, and support of 3D graphics.
In part one, MPR surveyed the collection of architectural components making up the core’s ISA. Part two focuses on the core’s implementation.
Microprocessor Report readers can access the full story (7 pages; 5 figures) here: www.mdronline.com/mpr/h/2005/1114/194601.html. To find out more about Microprocessor Report, please visit:
SPARC’s Still Going Strong
Kevin Krewell - Senior Editor
{11/14/2005}
We’ve been getting yearly updates from Fujitsu on its SPARC64 server processors for the past four Fall Processor Forums/Microprocessor Forums. Each year, the company extends the roadmap and reviews its steady, if underpublicized, progress in SPARC processor integration and process migrations. At Fall Processor Forum 2005, Mr. Takumi Maruyama, manager of Fujitsu Limited’s Processor Development Department 1 in the Enterprise Server Development Division, returned (he last presented in 2003) to give the latest roadmap update, extending the company’s SPARC roadmap out to 2008.
The present Fujitsu product is the 90nm SPARC64 V+, which runs at 2.16GHz. The next processor, finalizing development, is the SPARC64 VI, which is a dual-core processor. Fujitsu is still planning to deliver the chip in 2006; that situation hasn’t changed from last year’s presentation. The frequency goal for the SPARC64 VI is also still 2.4GHz.
The power requirements for the dual-core processor are considerably higher than for the single-core SPARC64 V, jumping to 120W from 65W. This isn’t an outrageous power number, considering that Fujitsu has doubled the cores and increased the clock frequency but stayed in the same 90nm process. All that logic results in a 540-million-transistor processor and the higher power. One architectural enhancement now officially included is that each SPARC64 VI core supports dual threads.
New at FPF05: Fujitsu revealed that its next processor after the SPARC64 VI will increase the number of cores on die to four. All those cores will also be dual threaded. Fujitsu’s 65nm process shrink (from 90nm) allows it to fit four cores and an unknown amount of shared L2 cache into one die.
Microprocessor Report readers can access the full story (3 pages; 3 figures) here: www.mdronline.com/mpr/h/2005/1114/194602.html. To find out more about Microprocessor Report, please visit:
