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AMD and Intel Harmonize on 64
Tom R. Halfhill - Senior Editor
{03/29/2004}
Intel says its new 64-bit x86 extensions will run the same 64-bit operating systems and almost all the same 64-bit application software as AMD’s 64-bit architecture. AMD says software compatibility should be no surprise, because Intel virtually reverse-engineered its 64-bit extensions from AMD64. An independent analysis by Microprocessor Report indicates both companies are correct. Except for a few minor differences, the two 64-bit architectures are identical.
MPR compared all the new instructions, modified instructions, deleted instructions, and modifications to the register files—including control registers, system registers, and registers visible to application programs. We also compared the memory-addressing schemes and many other architectural features, such as data-addressing modes, context-switching behavior, interrupt handling, and support for existing 16- and 32-bit x86 execution modes. In every case, we found Intel had patterned its 64-bit x86 architecture after AMD64 in almost every detail.
However, we also found a few differences that could make some software written for one 64-bit architecture incompatible with the other architecture. Some of these differences may be resolved in future 64-bit x86 processors, or even in future steppings of x86 processors already announced or on the market. In other cases, software can easily adapt to the differences by executing slightly different code, after first probing the CPU to learn which 64-bit extensions it supports.
MPR found nothing to contradict Intel’s promise that its 64-bit x86 processors will run the 64-bit operating systems developed for AMD64. At the same time, Intel’s reluctance to make a blanket guarantee about mutual 64-bit software compatibility is justified by the minor differences we discovered. Of course, that’s always the case when Intel or AMD introduces new x86 extensions—such as Intel’s SSE3 media extensions, which aren’t yet supported by AMD.
Despite the differences, Intel clearly derived its 64-bit architecture by reading AMD’s prerelease documentation for AMD64 and by testing AMD64 processors. Intel’s reverse-engineering of AMD64 marks a major turning point in the historical relationship between the companies. Although AMD has in the past introduced some innovations to the x86 architecture—the 3DNow multimedia extensions being a prime example—this is the first time AMD has truly steered the direction of the world’s most important microprocessor architecture, which Intel invented in 1978 and has closely guarded for 26 years.
Microprocessor Report readers can access the full story here (8 pages/5 graphics): www.mdronline.com/mpr/h/2004/0329/181301.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
GHz Considered Harmful
Peter Glaskowsky - Editor-in-Chief
{03/29/2004}
Intel will stop using clock frequency as the primary means of distinguishing among its many desktop and mobile processors. Instead, the company has introduced “Processor Numbers” reminiscent of those used by BMW for its automobiles—and by AMD for its Opteron chips. According to Intel, “GHz alone does not convey the full measure of processor capabilities,” and this shortcoming will become “more pronounced going forward.” Intel markets several different processor cores, each having various cache sizes and front-side bus speeds. Representing each chip by a gigahertz figure alone fails to convey the relative value of each member of Intel’s multiple product lines.
Intel’s processor numbers, unfortunately, fail to completely solve this problem, as they cannot be used to compare products from different product lines. Each chip continues to be represented by the combination of a brand name, such as “Pentium 4 processor,” with a single number. The numbers will initially come from three series—3xx, 5xx, and 7xx, just like BMW models—but each series may be associated with more than one product line.
The new approach eliminates the confusing letter suffixes applied to frequencies to indicate other features of each chip. It was difficult for end users to understand why a “2.8E GHz” processor would be faster than a “3.0A GHz” processor; the model numbers will more clearly express the relative capabilities within each product family.
We believe it would have been even more useful to assign processor numbers in a way that would allow value-based comparisons between product lines, so end users could more easily compare desktop processors to mobile processors, for example. We’ll have to wait to see how Intel’s approach works in the real world.
Microprocessor Report readers can access the full story here (1 page/1 graphics): www.mdronline.com/mpr/h/2004/0329/181302.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Serious Power for Embedded Systems
Peter Glaskowsky - Editor-in-Chief
{03/29/2004}
Back in the old days most embedded processors were derived from Unix workstation processors. There was little ongoing development of microprocessor cores specifically for embedded systems—and most embedded systems used inexpensive microcontrollers anyway.
The rise of the Internet and of digital entertainment changed all that. Almost all today’s embedded processors were designed specifically for embedded systems. No publication has done a better job of covering this revolution than MPR, and no industry conference has hosted more announcements of key products and technologies than our Embedded Processor Forum.
EPF 2004 takes place the week of May 17 at the luxurious Fairmont Hotel in San Jose, California. Our conference program includes 20 presentations of new products for the embedded-processor industry spread across five sessions—high-performance processors, software tools, embedded signal processing, video processing, and low-power processors. (Please visit www.mdronline.com/epf04 to see the complete program.)
The processors being announced at EPF span a wide range of power and performance characteristics, from ultralow-power cores for cellphone handsets to ultrapowerful chips created for high-end networking equipment. We’re especially pleased this year to be able to offer a session on software tools, responding to an increasingly common request from Forum attendees. Every year, it becomes more difficult for system developers to take full advantage of new architectures and instruction-set extensions; at EPF04, you’ll hear about new tools meant to solve this problem.
It’s no secret that the past few years have been difficult ones for events and publications in the computer industry. We have worked hard to continue delivering the same high-quality content in every issue of MPR and at each of our conferences. You may have noticed that the February issue of MPR, at 68 pages, was the largest we’ve ever published. We’re putting the same effort into EPF, with full-day seminars to deliver the latest information on the products and technologies in this market.
On the Monday before the conference, Tom Halfhill will present an updated version of his highly popular Microprocessors for Professionals seminar. This seminar can bring anyone up to speed on the fundamentals of microprocessor design. Thursday, after the conference, our own Max Baron and former MPR analyst Jim Turley will respectively examine all the most important low-power and high-performance embedded processors. These two seminars will cover the chips and cores announced at EPF, comparing them with competing products.
EPF04 has one of the best programs we’ve ever put together, but for it to be a great conference, we need your help. We hear that many companies have again freed up their travel and training budgets. EPF is a great way to get back up to speed on all the changes that have occurred in our industry over the past few years. If you can attend only one event this year, make it the Embedded Processor Forum. We hope to see you there.
To find out more about Microprocessor Report, please visit: www.mdronline.com.
ISSCC Presents Powerful Papers
Peter Glaskowsky - Editor-in-Chief
{03/22/2004}
At the 2004 International Solid-State Circuits Conference in February, San Francisco hosted an unusually robust series of presentations detailing circuit-design innovations in high-end microprocessors. The conference bills itself, justly, as “the foremost global forum for developments in integrated circuit and system design.” Session 3, the Processors track, included presentations from IBM and Intel about their latest designs.
Techniques to reduce power consumption were a major element of these presentations. Clock gating and other simple power-management techniques seem to be approaching their limits; chip designers are now tweaking each individual device in critical sections of their chips to match threshold voltage and other characteristics to the exact needs of the overall design. Chips are also being designed to operate as close to their thermal limits as possible, using closed-loop thermostatic regulation to maximize sustained throughput.
IBM’s presentations explained the way the company’s Power5 and PowerPC 970FX processors use multiple threshold voltages and multiple gate-oxide thicknesses to manage power consumption. Power5 is built in a 130nm process and uses three different threshold voltages. Even more variety is present in the PowerPC 970FX, built on IBM’s 90nm process. At ISSCC, IBM revealed that the 970FX uses four different VT values in its thin-oxide transistors and two more in thick-oxide transistors.
An interesting and entertaining panel on high-performance microprocessor design took place Tuesday evening at ISSCC with processor architects from AMD, Fujitsu, IBM, Intel, Stanford University, and Sun. The panel featured a lively discussion of the costs and benefits of ever-deeper processor pipelining. The panelists generally agreed that, over the next six years, chips will have to achieve most of their speedups from parallelism, not just higher clock rates.
Microprocessor Report readers can access the full story here (3 pages; 1 table): www.mdronline.com/mpr/h/2004/0322/181202.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Intel Addresses the 64-Bit Question
Peter Glaskowsky - Editor-in-Chief
{03/15/2004}
For a company that spends billions of dollars each year on research and development, Intel had surprisingly little to say at its recent Developer Forum in San Francisco. Intel offered updates to its Itanium roadmap, talked about wireless networking, and released the first official details of its support for the AMD64 extensions to the venerable x86 instruction set. Most of the IDF presentations merely rehashed information announced at previous forums, and the conference overall failed to shed enough light on some of the company’s most critical initiatives.
The 64-bit x86 content was limited to a few words in keynote speeches. AMD was never mentioned, but Intel privately confirmed that what Intel calls Extended Memory 64 Technology is nearly identical to AMD64. (We’re working on our own detailed comparison of the AMD and Intel extensions for publication in an upcoming issue of Microprocessor Report.)
The IDF roadmap update for the Itanium processor family for 2004 shows new members that have faster cores and more cache. Fanwood will offer a 1.6GHz clock rate and 3M of on-chip L3 cache. LV Fanwood will run at 1.2GHz and has the same L3 cache size but will consume less power, due to its lower operating voltage. Both these parts will be available by the end of the year. Intel has also promised to ship a new version of its Madison processor this year, upgraded to 9M of L3 cache and a 1.7GHz clock rate.
Intel’s plans to develop liquid crystal on silicon (LCOS) display components were a highlight of IDF. Intel’s LCOS devices are chip-scale liquid-crystal displays (LCD) less than an inch across. A rear-projection television can be built from a light source, projection optics, LCOS chips, and associated control electronics. In principle, such a system can cost much less than a full-size LCD with its own drive circuitry. Intel’s proven ability to manufacture complex silicon chips in high quantity will give it instant credibility as it seeks to expand its business into this new area. We can only hope that future IDFs present an equally crisp, clear picture of Intel’s other chip-development efforts.
Microprocessor Report readers can access the full story here (3 pages; 1 table): www.mdronline.com/mpr/h/2004/0315/181101.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Sun Rolls Forward With Rock
Peter Glaskowsky - Editor-in-Chief
{03/08/2004}
At its February analyst event, Sun Microsystems made its first public comments about Rock, the next multicore processor in the company’s Throughput Computing roadmap. Rock will be the first processor from Sun—and the first announced chip from any company—intended to deliver both high throughput on multithreaded workloads and high performance on applications having as few as one active thread.
Rock appears on Sun’s revised roadmap after Niagara, an eight-core processor with four-way multithreading on each core. Niagara will work well in database systems, web servers, and other environments where hundreds of tasks are pending at each moment. Rock is meant to work well in these systems as well as in the workstations and application servers where Sun’s UltraSparc is currently used.
Sun is showing signs of renewed vigor, claiming to have the industry’s highest-volume 64-bit enterprise server processor (UltraSparc III), a strong low-end server line that includes both Xeon and Opteron models, and the industry’s most successful 64-bit operating system (Solaris). We’re still not sure if Sun has the resources to support all the different processors it is currently developing, but the company seems to have a good understanding of what it—and its customers—needs in coming years.
Microprocessor Report readers can access the full story here (<1 page): www.mdronline.com/mpr/h/2004/0308/181002.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
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